The architecture profession, like many other design professions, is being revolutionized through the usage and development of computers. Both computer hardware and software are reaching levels of high development in the area of graphics. Even though graphic systems are becoming more sophisticated, there is no current linkage of textual information with graphics. Architectural projects consist of both text (specifications) and graphics (working drawings). Consequently, this creative project develops a computer software system (series of programs) for linking and unifying text information (specifications) with working drawings. / Department of Architecture

This thesis describes the design and implementation of a system called the Model Generator that graphically models digital system specifications expressed in English. This research is part of the ASPIN project which has a long-term goal of providing an automated system for digital system synthesis from informal specifications. Because of the versatility of the English language, there can be more than one interpretation of specification sentences. So before these specifications are synthesized into formal models, it is necessary to obtain validation of their interpretation from the specification author. The specification sentences are mapped into a common knowledge representation, called conceptual graphs, by first parsing and then semantically analyzing them. The Model Generator then uses the conceptual graphs to generate a graphical model representing the meaning of the English specification sentence. This is done in two stages. First, the commands for drawing the icons used for the graphical representation are assembled by consulting an Interpretation Library and a conceptual type hierarchy. In the second stage, the icons used in the representation are displayed using an X-Windows interface. The Model Generator has been implemented in the C programming language under the X-Windows environment. / Master of Science

by Siu Hing Kee Stanley. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1994. / Includes bibliographical references (leaves 87-88). / Abstract --- p.ii / Acknowledgments --- p.iii / Chapter 1 --- Introduction --- p.1-1 / Chapter 1.1 --- Introduction --- p.1-1 / Chapter 1.2 --- Background --- p.1-2 / Chapter 1.3 --- Thesis Organization --- p.1-4 / Chapter 2 --- Synthesis of Common Structures in a Microcontroller --- p.2-1 / Chapter 2.1 --- Limitation of Synthesis Tools --- p.2-1 / Chapter 2.2 --- Synthesizable VHDL for Common Structures --- p.2-2 / Chapter 2.2.1 --- Counter --- p.2-3 / Chapter 2.2.2 --- Set-Reset Latch --- p.2-6 / Chapter 2.2.3 --- D Latch --- p.2-9 / Chapter 2.2.4 --- D Flip-flop --- p.2-12 / Chapter 2.2.5 --- Multiplexor --- p.2-13 / Chapter 2.2.6 --- Shift Register --- p.2-15 / Chapter 2.2.7 --- Signal Affected by Two Signal Edges --- p.2-18 / Chapter 2.2.8 --- Combinational Feedback --- p.2-19 / Chapter 2.2.9 --- Short Pulses --- p.2-21 / Chapter 2.2.10 --- Register Transfer Logic --- p.2-22 / Chapter 2.2.11 --- Status Flag --- p.2-26 / Chapter 2.2.12 --- Register Access --- p.2-30 / Chapter 2.2.13 --- Clock Divider --- p.2-34 / Chapter 2.2.14 --- Communication among Processes --- p.2-36 / Chapter 3 --- Synthesis of Components of a Microcontroller --- p.3-1 / Chapter 3.1 --- Timer --- p.3-1 / Chapter 3.2 --- Serial Peripheral Interface (SPI) --- p.3-9 / Chapter 3.3 --- Serial Communication Interface (SCI) --- p.3-16 / Chapter 3.4 --- Parallel I/O Port --- p.3-21 / Chapter 3.5 --- 6805CPU --- p.3-22 / Chapter 3.5.1 --- State Counter --- p.3-23 / Chapter 3.5.2 --- Instruction Decoding and Execution Unit --- p.3-24 / Chapter 3.5.3 --- Interrupt Logic --- p.3-25 / Chapter 3.5.4 --- Instruction Register --- p.3-27 / Chapter 4 --- VHDL Coding and Synthesis --- p.4-1 / Chapter 4.1 --- Controlling Synthesis by VHDL Coding --- p.4-1 / Chapter 4.1.1 --- Structure Control --- p.4-2 / Chapter 4.1.2 --- Feedback Path Control --- p.4-2 / Chapter 4.1.3 --- Control of Use of Storage --- p.4-2 / Chapter 4.1.4 --- Timing Control --- p.4-3 / Chapter 4.2 --- Consequences of the Writing Guidelines --- p.4-5 / Chapter 5 --- Interface Tool for Generation of VHDL for a Microcontroller --- p.5-1 / Chapter 5.1 --- Features --- p.5-1 / Chapter 5.2 --- Construction --- p.5-1 / Chapter 5.3 --- Illustration --- p.5-3 / Chapter 5.4 --- Data Structure --- p.5-5 / Chapter 5.4.1 --- Design List --- p.5-6 / Chapter 5.4.2 --- Instance Data --- p.5-6 / Chapter 5.4.3 --- Instance List --- p.5-8 / Chapter 5.4.4 --- Register Data --- p.5-9 / Chapter 5.4.5 --- Dialogs and Functions --- p.5-10 / Chapter 5.5 --- VHDL Generator for Individual Component --- p.5-11 / Chapter 5.6 --- VHDL Generator for the Whole Microcontroller --- p.5-14 / Chapter 6 --- Conclusion --- p.6-1 / Bibliography --- p.B-1 / Appendix --- p.A-1