The thesis deals with an influence of the errors caused by utilization of the switched-current (SI) approach in the delta-sigma modulators. The basic block of the SI technique is current memory cell (CMC). The analysis of the errors starts with the design of the CMC using CADENCE software and AMIS CMOS 0.7 um technology. Based upon analysis of the CMC no ideal transfer function and advanced techniques of their behavior modeling are depicted. The mathematical models were made and implemented using MATLAB SIMULINK software. The models are very universal. Therefore, it is possible to analyze various structures of the delta-sigma modulators using demanded technology. The influence of the SI technique approach errors sources, on the modulators behavior with the CMC of the 1st and 2nd generation, is concluded at the end.