OFDM (Orthogonal Frequency Division Multiplexing) technology, due to its longer symbol duration that decease the amount of dispersion in time caused by multipath delay spread, has been widely used in many advanced digital communication systems such as DVB (Digital Video Broadcast), WLAN (Wireless Local Area Network), and UWB (Ultra Wide Band). How to realize efficient OFDM systems has been a very important issue for either academic or industry fields in recent years. This thesis aims to explore the VLSI implementation of the OFDM system targeted on its application on the wildly popular IEEE802.11a WLAN systems. An efficient OFDM architecture design involves the algorithm exploration and the tradeoff between the algorithm performance and hardware implementation. Therefore, in this thesis, a Matlab simulation platform for the IEEE802.11a baseband receiver is first built to refine several key synchronization algorithms including frame detection, timing recovery, carrier frequency offset, channel estimation as well as phase tracking under some given channel models. An excellent frame detection and timing recovery method is adopted such that nearly perfect synchronization can be achieved at SNR> 3. Furthermore, area-efficient architecture suitable for VLSI implementation for each synchronization module has also been proposed. In summary, 4 complex multipliers with 388 shift registers are required in our synchronization circuits. These modules are integrated with a core single-path radix-23 IFFT (Inverse Fast Fourier Transform) block to build a highly efficient WLAN baseband.