I många industriella tillämpningar används robotar för tunga och repetetiva uppgifter. För dessa tillämpningar är iterative learning control (ILC) ett sätt att fånga upp och utnyttja repeterbarheten för att förbättra någon form av referenseföljning. I det här examensarbetet har det tagits fram ett ramverk som ska hjälpa en användare att kunna untyttja ILC. Det visas handgripliga exempel på hur man enkelt kan avända ramverket. Övergången från den betydligt mer vanliga diskreta ILC algoritmen till det kontinuerliga tillvägagångssättet som anänds av ramverket underlättas av teroretisk  underbygga inställningsregler. Den uppnåeliga prestandan demonstreras med hjälp av ramverkets inbyggda plotfunktioner. / In many industrial applications robots are used for heavy and repetitive tasks. For these applications iterative learning control (ILC) is a way to capture the repetitive nature and use it to improve some kind of reference tracking. In this master thesis a framework has been developed to help a user getting started with ILC. Some hands-on examples are given on how to easily use the framework. The transition from the far more common discrete time domain to the continuous time domain used by the framework is eased by tuning theory. The achievable performance is demonstrated with the help of the built-in plot functions of the framework.

This thesis proposes and implements a flexible platform to perform Hardware-In-the-Loop (HIL) co-simulation using a Field-Programmable-Gate-Array (FPGA). The HIL simulations are performed with SystemModeler working as a software simulator and the FPGA as the co-simulator platform for the digital hardware design. The work presented in this thesis consists of the creation of: A communication library in the host computer, a system in the FPGA that allows implementation of different digital designs with varying architectures, and an interface between the host computer and the FPGA to transmit the data. The efficiency of the proposed system is studied with the implementation of two common digital hardware designs, a PID controller and a filter. The results of the HIL simulations of those two hardware designs are used to verify the platform and measure the timing and area performance of the proposed HIL platform.