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In the 1960s French mathematician George de Rham found a relationship between two invariants of knots. He found that there exist representations of the fundamental group of a knot into a group G of upper right triangular matrices in C with determinant one that is described exactly by the roots of the Alexander polynomial. I extended this result to find that the representations of the fundamental group of a link into G are described by the multivariable Alexander polynomial of the link.

In this thesis we introduce selected classes of matrices, whose entries are only numbers −1, 1, 0. We combine existing results from various fields of Mathematics and enrich them with specific examples and explanations, with the aim of making the understanding of the text easier. Thanks to that, the reader can comprehend the theory and look under the hood of non-trivial applications. We will start with introducing adjacency matrices and covering of complete graphs with complete bipartite graphs. Then we follow with Hadamard matrices and will show the conditions for their constructions. Incidence matrices of the set systems will help us solve the combinatorial problem of the Odd-town clubs. Finally, we will prove the Cayley formula about the spanning trees of the complete graph, using incidence matrices.

This thesis is concerned with enhancing analysis tools for evaluating the non-linear dynamics of rotor bearing systems and in particular those where non-linearity is likely to result in aperiodic or chaotic behaviour, such as rolling element bearing systems. The tool to be enhanced was the transfer matrix approach which has been extensively used in the past for analysing linear rotor bearing systems. However, its use for evaluating non-linear behaviour has been virtually non-existent. Hence, the major aim of the thesis is to extend transfer matrix capabilities to handle non-linear systems. To this end a harmonic balance transfer matrix technique capable of analysing non-linear systems with multiple pedestal supported bearings was first developed. However, this approach is restricted to periodic response. To enable the analysis of non-linear systems with non-periodic response and provide a stability check for the harmonic balance technique, a transient transfer matrix has also been developed. The softwares for both of these newly developed transfer matrix techniques have been successfully verified for various non-linear rotor bearing systems using an established system matrix based transient rotordynamics software as the yardstick. These developments have been published in refereed journals. To investigate systems with rolling element bearings, appropriate bearing modelling which incorporates angular contact and rolling element inertia needed to be developed and incorporated into transient analysis softwares. Theoretical results from this were compared to data obtained from an experimental test rig which was designed to represent the salient features of an F/A-18 aircraft mounted accessory drive. The rig allowed for variation of bearing preload, unbalance loading and bearing support stiffness and could be run up to 17,000rpm. Full details of the design and commissioning are presented. Results showed better agreement than linear analyses but significant differences were encountered. Errors were largely due to estimated bearing parameters, in particular bearing damping, which was found to be a sensitive variable, so that agreement between theory and experiment was mainly qualitative. Other sources of error were those associated with experimental measurement and limitations of the bearing modelling. Further improvement of the bearing model is needed if better quantitative agreement is to be obtained between the predictions and experiment.

Registration is a key component for computer-navigated robot-assisted surgery. Invasive approaches such as fiducial-based and surface matching with mechanical probes are common but ultrasound may provide a non-invasive alternative. If an A-mode ultrasound transducer can be used to percutaneously select data points on the bones, a registration can be determined without needing any incision. This study investigates selecting an A-mode ultrasound transducer, calibrating it, analyzing the ultrasound signal, and using it to register a phantom sawbone tibia and femur as well as cadaveric specimens. This study is performed in conjunction with MAKO Surgical Corp.'s Tactile Guidance System™ (TGS™) at their headquarters and at The South Florida Spine Clinic for cadaveric experiments. The results for phantom and cadaveric ultrasound registrations compared to a mechanical probe approach demonstrate that A-mode ultrasound registration is a viable option for registration of the bones of the knee.

Solving a system of linear and nonlinear equations lies at the heart of many scientific and engineering applications such as circuit simulation, applications in electric power networks, and structural analysis. The exponentially increasing complexity of these computing applications and the high cost of supercomputing force us to explore affordable high performance computing platforms. The ultimate goal of this research is to develop hardware friendly parallel processing algorithms and build cost effective high performance parallel systems using hardware in order to enable the solution of large linear systems. In this thesis, FPGA-based general hardware architectures of selected iterative methods and direct methods are discussed. Xilinx Embedded Development Kit (EDK) hardware/software (HW/SW) codesigns of these methods are also presented. For iterative methods, FPGA based hardware architectures of Jacobi, combined Jacobi and Gauss-Seidel, and conjugate gradient (CG) are proposed. The convergence analysis of the LNS-based Jacobi processor demonstrates to what extent the hardware resource constraints and additional conversion error affect the convergence of Jacobi iterative method. Matlab simulations were performed to compare the performance of three iterative methods in three ways, i.e., number of iterations for any given tolerance, number of iterations for different matrix sizes, and computation time for different matrix sizes. The simulation results indicate that the key to a fast implementation of the three methods is a fast implementation of matrix multiplication. The simulation results also show that CG method takes less number of iterations for any given tolerance, but more computation time as matrix size increases compared to other two methods, since matrix-vector multiplication is a more dominant factor in CG method than in the other two methods. By implementing matrix multiplications of the three methods in hardware with Xilinx EDK HW/SW codesign, the performance is significantly improved over pure software Power PC (PPC) based implementation. The EDK implementation results show that CG takes less computation time for any size of matrices compared to other two methods in HW/SW codesign, due to that fact that matrix multiplications dominate the computation time of all three methods while CG requires less number of iterations to converge compared to other two methods.<p> For direct methods, FPGA-based general hardware architecture and Xilinx EDK HW/SW codesign of WZ factorization are presented. Single unit and scalable hardware architectures of WZ factorization are proposed and analyzed under different constraints. The results of Matlab simulations show that WZ runs faster than the LU on parallel processors but slower on a single processor. The simulation results also indicate that the most time consuming part of WZ factorization is matrix update. By implementing the matrix update of WZ factorization in hardware with Xilinx EDK HW/SW codesign, the performance is also apparently improved over PPC based pure software implementation.

Core flooding is a commonly used experimental procedure in the petroleum industry. It involves pressurizing a reservoir rock and flowing fluid through it in the laboratory. The cylindrical rock, called a core, can be cut from the reservoir during a separate core drilling operation or a formation outcrop. A core flooding apparatus suitable for matrix acidizing was designed and assembled. Matrix acidizing is a stimulation technique in which hydrochloric acid (HCl) is injected down the wellbore below formation fracture pressure to dissolve carbonate (CaCO3) rock creating high permeability streaks called wormholes. The main components of the apparatus include a continuous flow syringe pump, three core holders, a hydraulic hand pump, two accumulators, a back pressure regulator, and two pressure transducers connected through a series of tubing and valves. Due to the corrosive nature of the acid, the apparatus features Hastelloy which is a corrosion resistant metal alloy. Another substantial feature of the apparatus is the ability to apply 3000psi back pressure. This is the pressure necessary to keep CO2, a product of the CaCO3 and HCl reaction, in solution at elevated temperatures. To perform experiments at temperature, the core holder is wrapped with heating tape and surrounded by insulation. Tubing is wrapped around a heating band with insulation to heat the fluid before it enters the core. A LabVIEW graphical programming code was written to control heaters as well as record temperature and pressure drop across the core. Other considerations for the design include minimizing footprint, operational ease by the user, vertical placement of the accumulators and core holders to minimize gravity effects, and air release valves. Core floods can be performed at varying injection rates, temperatures and pressures up to 5000psi and 250 degF. The apparatus can handle small core plugs, 1’’ diameter X 1’’ length, up to 4’’ X 20’’ cores. The equipment description includes the purpose, relevant features, and connections to the system for each component. Finally documented is the procedure to run a core flooding test to determine permeability and inject acid complete with an analysis of pressure response data.

Today's home network usually involves connecting multiple PCs and peripheral devices, such as printers and scanners, together in a network. This provides the benefit of allowing the PCs in the network to share Internet access and other resources. However, it is expected in the future, the home area network (HAN) will grow and extend to other home devices such as home entertainment systems (including digital TV, hi-fi stereo, etc.), appliances, webcam, security alarm system, etc. Connecting other home devices to a HAN provides users with many benefits not available in today's home networks. For example, home devices capable of connecting to the future HAN are able to share the content downloaded from broadband access anywhere in the home. Users can also have remote access and control of their home devices. To extend the home area network to all these different home devices, however, means that the traffic between the ISP and future HAN will be very different from the traffic generated by today’s home network. In today's home network, which consists mainly of multiple PCs, a best-effort approach is able to satisfy the need, since most of the traffic generated by PCs is not real-time in nature. However, in future HANs, it is anticipated that traffic generated from home devices requiring real-time applications such as multimedia entertainment systems, teleconferencing, etc. will occupy a large proportion of the traffic between the ISP and future HANs. In addition, given the variety of home devices that could potentially be added to future HANs, the amount and variety of traffic between the ISP and a future HAN will certainly be very different from today's home network that is dominated by Internet/data traffic. To allow HAN users of these real-time applications and various types of home devices to continue enjoying seamless experiences in using their home devices without noticing significant delays or unnecessary interruptions, it is important for the ISP to be able to effectively manage the channel to the home so that it can provide sufficient bandwidth to ensure high QoS for home applications. The aim of this thesis is to understand the types of traffic that will be expected and to develop an analytical model that will represent the traffic behaviour between the ISP and future HANs to understand how to manage the channel to provide high QoS. In this thesis, we use the continuous-time PH/M/n/m preemptive priority queue to model the traffic behaviour between the ISP and a future HAN. Three classes of traffic are defined in this model: real-time, interactive, and unclassified. Each of these three traffic classes receives a unique priority level. From the model one can approximate the amount of bandwidth required to be allocated for each traffic class for each household so that the total bandwidth required is minimized while the QoS requirements (delay and blocking probability) of the traffic generated by the home devices are met. Thus this model could potentially be used as a network planning tool for ISPs to estimate how much bandwidth they need to provide per household for homes that use home area network. Alternatively, it could also be used to estimate what quality of service (e.g. what is the mean delay and blocking probability expected) given a certain amount of bandwidth per household. / October 2006

Solving a system of linear and nonlinear equations lies at the heart of many scientific and engineering applications such as circuit simulation, applications in electric power networks, and structural analysis. The exponentially increasing complexity of these computing applications and the high cost of supercomputing force us to explore affordable high performance computing platforms. The ultimate goal of this research is to develop hardware friendly parallel processing algorithms and build cost effective high performance parallel systems using hardware in order to enable the solution of large linear systems. In this thesis, FPGA-based general hardware architectures of selected iterative methods and direct methods are discussed. Xilinx Embedded Development Kit (EDK) hardware/software (HW/SW) codesigns of these methods are also presented. For iterative methods, FPGA based hardware architectures of Jacobi, combined Jacobi and Gauss-Seidel, and conjugate gradient (CG) are proposed. The convergence analysis of the LNS-based Jacobi processor demonstrates to what extent the hardware resource constraints and additional conversion error affect the convergence of Jacobi iterative method. Matlab simulations were performed to compare the performance of three iterative methods in three ways, i.e., number of iterations for any given tolerance, number of iterations for different matrix sizes, and computation time for different matrix sizes. The simulation results indicate that the key to a fast implementation of the three methods is a fast implementation of matrix multiplication. The simulation results also show that CG method takes less number of iterations for any given tolerance, but more computation time as matrix size increases compared to other two methods, since matrix-vector multiplication is a more dominant factor in CG method than in the other two methods. By implementing matrix multiplications of the three methods in hardware with Xilinx EDK HW/SW codesign, the performance is significantly improved over pure software Power PC (PPC) based implementation. The EDK implementation results show that CG takes less computation time for any size of matrices compared to other two methods in HW/SW codesign, due to that fact that matrix multiplications dominate the computation time of all three methods while CG requires less number of iterations to converge compared to other two methods.<p> For direct methods, FPGA-based general hardware architecture and Xilinx EDK HW/SW codesign of WZ factorization are presented. Single unit and scalable hardware architectures of WZ factorization are proposed and analyzed under different constraints. The results of Matlab simulations show that WZ runs faster than the LU on parallel processors but slower on a single processor. The simulation results also indicate that the most time consuming part of WZ factorization is matrix update. By implementing the matrix update of WZ factorization in hardware with Xilinx EDK HW/SW codesign, the performance is also apparently improved over PPC based pure software implementation.

The main purpose of acid/water jetting treatments currently applied in the field is to clean up the filter cake formed during the drilling process and perhaps further stimulate the wellbore by creating wormholes if acid jetting is used in carbonate formation. This purpose can be achieved for the reason that the filter cake on the borehole can be mechanically broken by the high speed jetting action, and additionally, if acid is used, some materials in the filter cake can be dissolved, which can facilitate the mechanical breaking action. The knowledge of jetting effectiveness under various conditions is crucial for the purpose of optimizing the treatment design. In order to investigate quantitatively the effectiveness of acid/water jetting for filter cake cleanup and wellbore productivity enhancement, laboratory experiments were carried out under conditions similar to those in the field. Filter cake was deposited on the face of a 4 inch diameter core and then water or 15% HCl were used for jetting treatment. The original permeability, the permeability right after the drill-in fluid damage, and the permeability after the jetting treatment were measured and compared. The effect of overbalance pressure during the jetting treatment was investigated. CT scan was carried out for those cores that may have wormholes after the acid jetting treatment. An analysis of the mechanism for filter cake removal and wormhole creating during acid jetting treatment was proposed. It is discovered that acid jetting can effectively remove the filter cake by penetrating and lifting it from beneath, and efficient wormhole creation can only happen when the overbalance pressure during the acid jetting treatment is above a certain value. Based on this study, several suggestions for field applications were made.