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Analog Artificial Neurons and Digital Amplifiers: Challenging the Roles of Analog and Digital Circuit Architectures in Modern CMOS ProcessesBarton, Taylor S. 09 November 2023 (has links) (PDF)
As complimentary metal-oxide semiconductor (CMOS) technologies scale and field-effect transistor (FET) architectures change, the factors in deciding to utilize analog or digital transistor behaviors evolve. This thesis examines three case studies where traditionally analog or digital circuitry has dominated published works but I show that the opposite regime has significant benefits in scaled CMOS technologies. I present a highly digital operational amplifier (traditionally analog) and two artificial neurons (traditionally digital). In Chapters 2 and 3 I present a highly-digital five-stage zero-crossing-based amplifier which breaks the trade-off between slew rate and settling accuracy. I investigate the optimal charge pump design by analyzing the effects of the current scaling factor, number of current sources, maximum current value, and input amplitude on the settling performance including overshoot and settling time. I find that there exists an optimal number of stages that yields the fastest settling for a given total current and load capacitance. The proposed amplifier achieves a signal-to-noise ratio of 57 dB at a sampling rate of 40 MHz and consumes 1.45 mW under a 1V supply. In Chapters 4 and 5, I propose two novel analog artificial spiking neurons, operating in the voltage domain and phase domain respectively. The voltage domain neuron presented in Chapter 4 implements a novel fine-tuning method called neuromodulatory tuning which reduced the number of parameters to be tuned by four orders of magnitude as compared with traditional fine-tuning methods. Chapter 5 presents the design of a novel phase-domain neuron. Voltage domain neurons mimic biological neurons by integrating charge on a capacitor. I instead integrate phase in a voltage-controlled ring oscillator (VCO). I also propose a novel bidirectional switched-capacitor synapse which saves significant area compared to bidirectional current based synapses. The proposed neuron, synapse and weight memory occupy only 21x27um, and consume 134fJ/spike under a 0.35V supply.
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