<p>A new practical technique for estimating the junction temperature and the thermal resistance of an HBT was developed. The technique estimates an interval for the junction temperature. The main assumption in the new technique is that the junction temperature can be calculated from three separate phenomena: The thermal conduction of the substrate, the thermal conduction of the metal connecting the emitter to the via holes, the effects of the via holes on the substrate temperature. The main features of the new technique are: The junction temperature and the thermal resistance are calculated from a few physical properties and the layout of the transistors, the only required software tool is MATLAB, the calculation time is very short compared to a full 3D thermal simulation, and the technique is easy to use for the circuit designer. The new technique shows good accuracy, when applied to several InGaP/GaAs HBT’s from Caswell Technology, and compared to the results from other methods. All the results fall well within the estimated junction temperature intervals from the new technique. A practical parameter extraction method for the VBIC model was developed. This method is the first published practical parameter extraction technique for the VBIC model used on an InGaP/GaAs HBT, as far as the author knows. The main features of the extraction method are: Only a few common measurements are needed, it is easy and practical to use for the circuit designer, it has good accuracy with only a few iterations. No expensive and specialized parameter extraction software is required. The only software needed is a circuit simulator. The method includes the extraction of the bias dependent forward transit time. The extraction method was evaluated on a single finger, 1x40, InGaP/GaAs HBT from Caswell Technology. Only four iterations were required to fit the measurements very well. There is less than 1 % error in both the Ic-Vce and Vbe-Vce plots. The maximum magnitude and phase error in the whole frequency range up to 40GHz are less than 1.5 dB and 15 degrees. The method is also evaluated on a SiGe HBT. Models for a single finger and an 8-finger transistor were extracted. All the dc characteristics of the modeled transistors have less than 3.5 % error. Some amplitude and phase errors are observed in the s-parameters. The errors are caused by uncertainties in the calibration due to a worn calibration substrate, high temperature drift during the measurements, and uncertainties in the physical dimensions/properties caused by lack of information from the foundry. Overall, the extracted models fit the measurements quite well. A very linear class A power amplifier has been designed using the InGaP/GaAs HBT’s from Caswell technology. The thermal junction estimation technique developed has been used to make a very good thermal layout of the power amplifier. The estimated average junction temperature is 98.6°C above the ambient temperature of 45°C, with a total dissipated power of 6.4W. The maximum junction temperature difference between the transistor fingers is less than 11°C. The PA was constructed with a ‘bus bar’ power combinder at both input and output, and optimized for maximum gain with a 10% bandwidth. The PA had a maximum output power of 34.8dBm, a 1dB compression point of 34.5dBm, a the third order intercept point of 49.9dBm, and a PAE of 27.2% at 33dBm output power. </p><p> </p>

A new practical technique for estimating the junction temperature and the thermal resistance of an HBT was developed. The technique estimates an interval for the junction temperature. The main assumption in the new technique is that the junction temperature can be calculated from three separate phenomena: The thermal conduction of the substrate, the thermal conduction of the metal connecting the emitter to the via holes, the effects of the via holes on the substrate temperature. The main features of the new technique are: The junction temperature and the thermal resistance are calculated from a few physical properties and the layout of the transistors, the only required software tool is MATLAB, the calculation time is very short compared to a full 3D thermal simulation, and the technique is easy to use for the circuit designer. The new technique shows good accuracy, when applied to several InGaP/GaAs HBT’s from Caswell Technology, and compared to the results from other methods. All the results fall well within the estimated junction temperature intervals from the new technique. A practical parameter extraction method for the VBIC model was developed. This method is the first published practical parameter extraction technique for the VBIC model used on an InGaP/GaAs HBT, as far as the author knows. The main features of the extraction method are: Only a few common measurements are needed, it is easy and practical to use for the circuit designer, it has good accuracy with only a few iterations. No expensive and specialized parameter extraction software is required. The only software needed is a circuit simulator. The method includes the extraction of the bias dependent forward transit time. The extraction method was evaluated on a single finger, 1x40, InGaP/GaAs HBT from Caswell Technology. Only four iterations were required to fit the measurements very well. There is less than 1 % error in both the Ic-Vce and Vbe-Vce plots. The maximum magnitude and phase error in the whole frequency range up to 40GHz are less than 1.5 dB and 15 degrees. The method is also evaluated on a SiGe HBT. Models for a single finger and an 8-finger transistor were extracted. All the dc characteristics of the modeled transistors have less than 3.5 % error. Some amplitude and phase errors are observed in the s-parameters. The errors are caused by uncertainties in the calibration due to a worn calibration substrate, high temperature drift during the measurements, and uncertainties in the physical dimensions/properties caused by lack of information from the foundry. Overall, the extracted models fit the measurements quite well. A very linear class A power amplifier has been designed using the InGaP/GaAs HBT’s from Caswell technology. The thermal junction estimation technique developed has been used to make a very good thermal layout of the power amplifier. The estimated average junction temperature is 98.6°C above the ambient temperature of 45°C, with a total dissipated power of 6.4W. The maximum junction temperature difference between the transistor fingers is less than 11°C. The PA was constructed with a ‘bus bar’ power combinder at both input and output, and optimized for maximum gain with a 10% bandwidth. The PA had a maximum output power of 34.8dBm, a 1dB compression point of 34.5dBm, a the third order intercept point of 49.9dBm, and a PAE of 27.2% at 33dBm output power.