With ever shrinking geometries, growing metal density and increasing clock rate on chips, delay testing is becoming a necessity in industry to maintain test quality for speed-related failures. The purpose of delay testing is to verify that the circuit operates correctly at the rated speed. However, functional tests for delay defects are usually unacceptable for large scale designs due to the prohibitive cost of functional test patterns and the difficulty in achieving very high fault coverage. Scan-based delay testing, which could ensure a high delay fault coverage at reasonable development cost, provides a good alternative to the at-speed functional test. This dissertation addresses several key challenges in scan-based delay testing and develops efficient Automatic Test Pattern Generation (ATPG) and Design-for-testability (DFT) algorithms for delay testing. In the dissertation, two algorithms are first proposed for computing and applying transition test patterns using stuck-at test vectors, thus avoiding the need for a transition fault test generator. The experimental results show that we can improve both test data volume and test application time by 46.5% over a commercial transition ATPG tool. Secondly, we propose a hybrid scan-based delay testing technique for compact and high fault coverage test set, which combines the advantages of both the skewed-load and broadside test application methods. On an average, about 4.5% improvement in fault coverage is obtained by the hybrid approach over the broad-side approach, with very little hardware overhead. Thirdly, we propose and develop a constrained ATPG algorithm for scan-based delay testing, which addresses the overtesting problem due to the possible detection of functionally untestable faults in scan-based testing. The experimental results show that our method efficiently generates a test set for functionally testable transition faults and reduces the yield loss due to overtesting of functionally untestable transition faults. Finally, a new approach on identifying functionally untestable transition faults in non-scan sequential circuits is presented. We formulate a new dominance relationship for transition faults and use it to help identify more untestable transition faults on top of a fault-independent method based on static implications. The experimental results for ISCAS89 sequential benchmark circuits show that our approach can identify many more functionally untestable transition faults than previously reported. / Ph. D.

Pliocene to Pleistocene glacial-marine deposits adjacent to the Fairweather Ground basement in the Gulf of Alaska are the focus for seismic interpretation using public domain seismic reflection data. The late Tertiary and early Quaternary sections of the Yakataga Formation record a glacial/ interglacial climate change sequence with increasing rates of sedimentation (175 meters per million years to 4000 meters per million years). The foreland basin sediment load is deposited onto the Yakutat block, a microplate that takes up the strike-slip to convergent movement with respect to North America and Pacific plates. Tectonic activity during the last 5 million years has resulted in Eocene rock exposed at the sea floor. High resolution bathymetry data adjacent to the Yakutat microplate is utilized to 1) observe the results of deformation from Pacific plate loading on the Yakutat microplate and 2) interpret the Transition fault as an active thrust to oblique thrust fault.