This thesis presents an automatic tuning circuit that it is focused on compensation for the filter¡¦s frequency error resulting from the variation of fabrication process, supply voltage and temperature. We utilize a tunable operational transconductance amplifier and a capacitor to form a single-time constant circuit (STC). When we input a reference signal to this circuit, the output of STC circuit can produce a controllable delay time clock. The tuning circuit uses the constant delay time to tune the frequency of the filter. The design of the STC circuit is simple and it has less chip area. All circuits are designed by using the parameters of TSMC 0.35um mixed signal process, and the supply voltage is 3V. The simulation result shows that the filter¡¦s 3-dB frequency error can be controlled by less than 7% as the filter is under the condition of over a range of supply voltages(¡Ó10¢H), operating temperatures(-20 ¢Jto 70¢J ) and five models of SPICE model.

MOSFET-C filters is popular in analog filters, the major reason is the simplicity. They are easily implemented with opamps and have similar architectures to active RC filters [1], this saves much of the design time. The frequency response of analog continuous time filters is determined by resistors, capacitors, inductors or transconductors. However, the process variation, temperature drift and aging, make the integrated RC time constants vary about 30 percent [2]~[3]. We proposed a switched-capacitor tuning circuit , which can be used in MOSFET-C Filter and the novel tuning circuit doesn¡¦t need off chip capacitor. The novel circuit has following advantages (1). Small chip size. (2). Simplicity (3). Low reference clock frequency.

In this thesis, a simple on-chip automatic frequency tuning circuit is presented. The tuning circuit is improved from voltage-controlled filter (VCF) frequency tuning circuit. We use a single time constant (STC) circuit to substitute the voltage-controlled filter. The STC circuit can produce a controllable delay time clock. The tuning circuit uses the constant delay time to tune the frequency of the filter. The design of a STC circuit is easy. Because the circuit is simple, the tuning circuit has less chip area and less power consumption. The circuit has been fabricated with 0.35£gm CMOS technology. It operates with supply voltages ¡Ó1.5 V. The filter operates at a 3-dB frequency of 10MHz. In simulation, the frequency tuning circuit has a 3-dB frequency tuning error of less than 12% and the power consumption less than 9.05mW over a range of supply voltages (¡Ó10%), operating temperatures (-20¢J to 70¢J) and five models of SPICE model.

Within the master’s thesis there is comparison of different structures of ARC oscillators with respect to their harmonic distortion. Individual blocks of oscillator are analyzed. Attention is paid to choosing and design of suitable ARC filter structure and possibilities of its tuning. Also possibilities of stabilization of amplitude are analyzed. Different types of controlled amplifiers and circuits for controlling of their amplification are discussed. Next captures are focused to designing and simulation of the ARC oscillator. The oscillator can be tuned in the frequency range from 100 Hz to 20 kHz with harmonic distortion smaller than 1%. At the end of the thesis, practical realization of the proposed circuit is described. Also results of the measurement of parameters of the oscillator are given.