In the age of system-on-chip designs, design complexity of systems increases continuingly. This results in difficulty of design convergence. In design exploration of system architectures, we need to design, specify, and verify system designs effectively. By employing an architecture description language (ADL), we can effectively support specification and verification of system level designs. Existing ADLs have certain de-efficiencies in specification capabilities. We designed and improved specification capabilities in our architecture description language. Specification techniques in our ADL include behavioral description, structural description, regular structure description, built-in architecture feature description, and data integration description. In this thesis research, we focus on supporting verification capability of our ADL. We designed a simulator of the ADL. The simulation mechanisms include language input design, simulation data structure construction, behavioral simulation, structural simulation, regular architecture simulation, built-in architecture feature simulation, and data integration mechanism. With the ADL simulator, we can verify functionality and performance of architecture designs specified in the ADL. Simulation results can thus be used to guide design exploration and help design convergence.