Micro-Electro-Mechanical Systems (MEMS) varactors have the potential to replace conventional varactor diodes, due to their high loss and non-linearity, in many applications such as phase shifters, oscillators, and tunable filters. The objective of this thesis is to develop novel MEMS varactors to improve the capacitance tuning ratio, linearity, and quality factor. Several novel varactor configurations are developed, analyzed, fabricated and tested. They are built by using standard MEMS fabrication processes, as well as monolithic integration techniques in CMOS technology. The first capacitor consists of two movable plates, loaded with a nitride layer that exhibits an analog continuous capacitance tuning ratio. To decrease the the parasitic capacitance, a trench in the silicon substrate under the capacitor is adopted. The use of an insulation dielectric layer on the bottom plate of the MEMS capacitor increases the capacitors’ tuning ratio. Experimental and theoretical results are presented for two versions of the proposed capacitor with different capacitance values. The measured capacitance tuning ratio is 280% at 1 GHz. The proposed MEMS vararctor is built using the MetalMUMPs process. The second, third, and fourth capacitors have additional beams that are called carrier beams. The use of the carrier beams makes it possible to obtain an equivalent nonlinear spring constant, which increases the capacitors’ analog continuous tuning ratio. A lumped element model and a continuous model of the proposed variable capacitors are developed. The continuous model is simulated by commercial software. A detailed analysis for the steady state of the capacitors is presented. The measured capacitance tuning ratios of these three capacitors are 410%, 400% and 470%, respectively at 1 GHz. Also, the selfresonance frequency is measured and found to exceed 11 GHz. The proposed MEMS variable capacitors are built by the PolyMUMPs process. The fifth novel parallel-plate MEMS varactor has thin-film vertical comb actuators as its driver. Such an actuator can vertically displace both plates of the parallel-plate capacitor. By making use of the fringing field, this actuator exhibits linear displacement behavior, caused by the induced electrostatic force of the actuator’s electrodes. The proposed capacitor has a low parasitic capacitance and linear deflection due to the mechanically connected and electrically isolated actuators to the capacitor’s parallel-plates. The measured tuning capacitance ratio is 7:1 (600%) at 1 GHz. The fabricated MEMS varactor exhibits a self resonance frequency of 9 GHz and built by MetalMUMPs process. The sixth parallel-plate MEMS varactor exhibits a linear response and high tuning capacitance ratio. The capacitor employs the residual stress of the chosen bi-layer, and the non-linear spring constants from the suspended cantilevers to obtain a non-linear restoring force that compensates for the nonlinear electrostatic force induced between the top and bottom plates. Two existing techniques are used to widen the tuning range of the proposed capacitor. The first technique is to decrease the parasitic capacitance by etching the lossy substrate under the capacitor’s plates. The second technique is employed to increase the capacitance density, where the areas between the top and bottom plates overlap, by applying a thin film of dielectric material, deposited by the atomic layer deposition (ALD) technique. The measured linear continuous tuning ratio for the proposed capacitor, built in the PolyMUMPs process, is 5:1 (400%). The seventh and eighth MEMS variable capacitors have plates that curl up. These capacitors are built in 0.35 μm CMOS technology from the interconnect metallization layers. The plates of the presented capacitors are intentionally curled upward to control the tuning performance. A newly developed maskless post-processing technique that is appropriate for MEMS/CMOS circuits is proposed. it consists of dry and wet etching steps, developed to integrate the proposed MEMS varactors in CMOS technology. Mechanically, the capacitors are simulated by the finite element method in ANSYS, and the results are compared with the measured results. The seventh capacitor is a tri-state structure that exhibits a measured tuning range of 460% at 1 GHz with a flat capacitance response that is superior to that of conventional digital capacitors. The proposed capacitor is simulated in HFSS and the extracted capacitance is compared with the measured capacitance over a frequency range of 1 GHz to 5 GHz. The eighth capacitor is an analog continuous structure that demonstrates a measured continuous tuning range of 115% at 1 GHz with no pull-in. The measured quality factor for both CMOSbased capacitors is more than 300 at 1.5 GHz. The proposed curled-plate capacitors have a small area and can be realized to build a System-on-Chip (SoC). Finally, a tunable band pass filter that utilizes the MEMS variable capacitors in 0.18 μm CMOS technology from TSMC is designed, modeled and fabricated.

Micro-Electro-Mechanical Systems (MEMS) varactors have the potential to replace conventional varactor diodes, due to their high loss and non-linearity, in many applications such as phase shifters, oscillators, and tunable filters. The objective of this thesis is to develop novel MEMS varactors to improve the capacitance tuning ratio, linearity, and quality factor. Several novel varactor configurations are developed, analyzed, fabricated and tested. They are built by using standard MEMS fabrication processes, as well as monolithic integration techniques in CMOS technology. The first capacitor consists of two movable plates, loaded with a nitride layer that exhibits an analog continuous capacitance tuning ratio. To decrease the the parasitic capacitance, a trench in the silicon substrate under the capacitor is adopted. The use of an insulation dielectric layer on the bottom plate of the MEMS capacitor increases the capacitors’ tuning ratio. Experimental and theoretical results are presented for two versions of the proposed capacitor with different capacitance values. The measured capacitance tuning ratio is 280% at 1 GHz. The proposed MEMS vararctor is built using the MetalMUMPs process. The second, third, and fourth capacitors have additional beams that are called carrier beams. The use of the carrier beams makes it possible to obtain an equivalent nonlinear spring constant, which increases the capacitors’ analog continuous tuning ratio. A lumped element model and a continuous model of the proposed variable capacitors are developed. The continuous model is simulated by commercial software. A detailed analysis for the steady state of the capacitors is presented. The measured capacitance tuning ratios of these three capacitors are 410%, 400% and 470%, respectively at 1 GHz. Also, the selfresonance frequency is measured and found to exceed 11 GHz. The proposed MEMS variable capacitors are built by the PolyMUMPs process. The fifth novel parallel-plate MEMS varactor has thin-film vertical comb actuators as its driver. Such an actuator can vertically displace both plates of the parallel-plate capacitor. By making use of the fringing field, this actuator exhibits linear displacement behavior, caused by the induced electrostatic force of the actuator’s electrodes. The proposed capacitor has a low parasitic capacitance and linear deflection due to the mechanically connected and electrically isolated actuators to the capacitor’s parallel-plates. The measured tuning capacitance ratio is 7:1 (600%) at 1 GHz. The fabricated MEMS varactor exhibits a self resonance frequency of 9 GHz and built by MetalMUMPs process. The sixth parallel-plate MEMS varactor exhibits a linear response and high tuning capacitance ratio. The capacitor employs the residual stress of the chosen bi-layer, and the non-linear spring constants from the suspended cantilevers to obtain a non-linear restoring force that compensates for the nonlinear electrostatic force induced between the top and bottom plates. Two existing techniques are used to widen the tuning range of the proposed capacitor. The first technique is to decrease the parasitic capacitance by etching the lossy substrate under the capacitor’s plates. The second technique is employed to increase the capacitance density, where the areas between the top and bottom plates overlap, by applying a thin film of dielectric material, deposited by the atomic layer deposition (ALD) technique. The measured linear continuous tuning ratio for the proposed capacitor, built in the PolyMUMPs process, is 5:1 (400%). The seventh and eighth MEMS variable capacitors have plates that curl up. These capacitors are built in 0.35 μm CMOS technology from the interconnect metallization layers. The plates of the presented capacitors are intentionally curled upward to control the tuning performance. A newly developed maskless post-processing technique that is appropriate for MEMS/CMOS circuits is proposed. it consists of dry and wet etching steps, developed to integrate the proposed MEMS varactors in CMOS technology. Mechanically, the capacitors are simulated by the finite element method in ANSYS, and the results are compared with the measured results. The seventh capacitor is a tri-state structure that exhibits a measured tuning range of 460% at 1 GHz with a flat capacitance response that is superior to that of conventional digital capacitors. The proposed capacitor is simulated in HFSS and the extracted capacitance is compared with the measured capacitance over a frequency range of 1 GHz to 5 GHz. The eighth capacitor is an analog continuous structure that demonstrates a measured continuous tuning range of 115% at 1 GHz with no pull-in. The measured quality factor for both CMOSbased capacitors is more than 300 at 1.5 GHz. The proposed curled-plate capacitors have a small area and can be realized to build a System-on-Chip (SoC). Finally, a tunable band pass filter that utilizes the MEMS variable capacitors in 0.18 μm CMOS technology from TSMC is designed, modeled and fabricated.

The Class-E topology was presented as a single-switch power amplifier with high efficiency at the optimum condition, where the switch enjoys zero-voltage switching (ZVS) and zero-voltage-derivative switching (ZDS). It is also used in MHz dc-dc converters, and in inverters for wireless power transfer, induction heating, and plasma pulsing. The load current in these applications usually varies over a range. Efficiency of a conventional Class-E design degrades dramatically due to the hard switching beyond the optimum conditions. Keeping ZVS with load change in a Class-E topology is preferred within the load range. Soft switching with load variation is realized by duty cycle modulation with additional transformer, matching network, or resistance compression network. Since two ZVS requirements need to be satisfied in a conventional Class-E design, at least two parameters are tuned under load variation. Thus, changing switching frequency, duty cycle, and component values were used. Impressively, a load-independent Class-E inverter design was presented in 1990 for maintaining ZVS and output voltage under a given load change without tuning any parameters, and it was validated with experimental results recently. The operating principle of this special design (inconsistent with the conventional design) is not elucidated in the published literatures. Load-independency illucidation by a Thevenin Model – A Thevenin model is then established (although Class-E is a nonliear circuit) to explain the load-independency with fixed switching frequency and duty cycle. The input block of a Class-E inverter (Vin, Lin, Cin, and S) behaves as a fixed voltage source vth1 and a fixed capacitive impedance Xth1 in series at switching frequency. When the output block (Lo and Co) is designed to compensate Xth1, the output current phase is always equal to the phase of vth1 with resistive load (satisfies the ZVS requirement of a load-independent design). Thus, soft switching is maintained within load variation. Output voltage is equal to vth1 since Xth1 is canceled, so that the output voltage is constant regardless of output resistance. Load-independency is achieved without adding any components or tuning any parameters. Sequential design and tuning of a load-independent ZVS Class-E inverter with constant voltage based on Thevenin Model - Based on the model, it's found that each circuit parameter is linked to only one of the targeted performance (ZVS, fixed voltage gain, and load range). Thus, the sequential design equations and steps are derived and presented. In each step, the desired performance (e.g. ZVS) now could be used to check and tune component values so that ZVS and fixed voltage gain in the desired load range is guaranteed in the final Class-E inverter, even when component values vary from the expectations. The Thevenin model and the load-independent design is then extended to any duty cycles. A prototype switched at 6.78 MHz with 10-V input, 11.3-V output, and 22.5-W maximum output power was fabricated and tested to validate the theory. Soft switching is maintained with 3% output voltage variation while the output power is reduced tenfold. A load-independent ZVS Class-E inverter with constant current by combining constant voltage design and a trans-susceptance network - A load-independent ZVS Class-E inverter with constant current under load variation is then presented, by combining the presented design (generating a constant voltage) and a trans-susceptance network (transferring the voltage to current). The impact of different types and the positions of the networks are discussed, and LCL network is selected so that both constant current and soft switching are maintained within the load variation. The operation principle, design, and tuning procedures are illustrated. The trade-off between input current ripple, output current amplitude, and the working load range is discussed. The expectations were validated by a design switched at 6.78 MHz with 10-V input, 1.4-A output, and 12.6-W maximum output power. Soft switching is maintained with 16% output current varying over a 10:1 output power range. A "ZVS" Class-E dc-dc converter by adding a diode rectifier bridge and compensate the induced varying capacitance at full-load condition - The load-independent Class-E design is extended to dc-dc converter by adding a diode rectifier bridge followed by the Class-E inverter. The equivalent impedance seen by the inverter consists of a varying capacitance and a varying resistance when the output changes. As illustrated before, ZVS and constant output can only be maintained with resistive load. Since the varying capacitance cannot be compensated for the whole load range, performance with using different compensation is discussed. With the selected full-load compensation, ZVS is achieved at full load condition and slight non-ZVS occurs for the other load conditions. The expectation was validated by a dc-dc converter switched at 6.78 MHz with 11 V input, 12 V output, and 22 W maximum output power. ZVS (including slight non-ZVS) is maintained with 16% output voltage variation over 20:1 output power range. Design of variable Capacitor by connecting two voltage-sensitive capacitors in series and controlling the bias voltage of them - The equivalent varying capacitance in the Class-E dc-dc converter can be compensated in the whole load range only with variable component. The sensitivity of a Class-E power conversion can also be improved by using variable capacitors. Thus, a Voltage Controlled Capacitor (VCC) is presented, based on the intrinsic property of Class II dielectric materials that permittivity changing much with electric field. Its equivalent circuit consists of two identical Class II capacitors in series. By changing the voltage of the common point of the two capacitors (named as control voltage), the two capacitance and the total capacitance are both changed. Its operation principle, measured characteristic, and the SPICE model are illustrated. The capacitance changes from 1 μF to 0.2 μF with a control voltage from 0 V to 25 V, resulting a 440% capacitance range. Since the voltage across the two capacitors (named as output voltage) also affects one of the capacitance when control voltage is applied, the capacitance range drops to only 40% with higher bias in the output voltage. Thus, a Linear Variable Capacitor (LVC) is presented. The equivalent circuit is the same as VCC, while one of the capacitance is designed much higher to mitigate the effect of output voltage. The structure, operational principle, required specifications, design procedures, and component selection were validated by a design example, with 380% maximum capacitance range and less than 20% drop in the designed capacitor voltage range. This work contributes to • Analytical analysis and Thevenin Model in load-independent Class-E power conversion • Variable capacitance with wide range / Doctor of Philosophy / The Class-E topology was presented as a single-switch power amplifier with high efficiency at the optimum condition. Efficiency of a conventional Class-E design degrades with load variation dramatically due to the hard switching beyond the optimum conditions. Since two requirements need to be satisfied for soft switching in a conventional Class-E design, at least two parameters are tuned under load variation. Impressively, a load-independent Class-E inverter design was presented for maintaining Zero-Voltage-Switching (ZVS) and output voltage under a given load change without tuning any parameters, and it was validated with experimental results recently. A Thevenin model is established in this work to explain the realization of load-independency with fixed switching frequency and duty cycle. Based on that, a sequential design and tuning process is presented. A prototype switched at 6.78 MHz with 10-V input, 11.3-V output, and 22.5-W maximum output power was fabricated and tested to validate the theory. Soft switching is maintained with 3% output voltage variation while the output power is reduced tenfold. A load-independent ZVS Class-E inverter with constant current under load variation is then presented, by combining the presented design and a trans-susceptance network. The expectations were validated by a design switched at 6.78 MHz with 10-V input, 1.4-A output, and 12.6-W maximum output power. Soft switching is maintained with 16% output current varying over a 10:1 output power range. The load-independent Class-E design is extended to dc-dc converter by adding a diode rectifier bridge, inducing a varying capacitance. With the selected full-load compensation, ZVS is achieved at full load condition and slight non-ZVS occurs for the other load conditions. The expectation was validated by a dc-dc converter switched at 6.78 MHz with 11 V input, 12 V output, and 22 W maximum output power. ZVS (including slight non-ZVS) is maintained with 16% output voltage variation over 20:1 output power range. The varying capacitance in the Class-E dc-dc converter needs variable component to compensate. Thus, a Voltage Controlled Capacitor (VCC) is presented. The capacitance changes from 1 μF to 0.2 μF with a control voltage from 0 V to 25 V, resulting a 440% capacitance range. The capacitance range drops to only 40% with higher bias in the output voltage. Thus, a Linear Variable Capacitor (LVC) is presented, with 380% maximum capacitance range and less than 20% drop in the designed capacitor voltage range.

No description available.

No description available.

La tendance actuelle vers la miniaturisation des circuits électroniques a poussé vers ledéveloppement des systèmes sur puce (SoC : System on Chip) contenant plusieurs composants. Cescomposants réalisant des fonctions variées, ont besoin de différentes tensions d’alimentation fourniesà l’aide de plusieurs convertisseurs DC/DC connectés à l’alimentation du SoC. Actuellement, laplupart des circuits électroniques dans les applications portables contiennent des convertisseursDC/DC conventionnels utilisant une inductance pour stocker transitoirement l’énergie électrique.L’inductance étant un composant passif difficilement intégrable, ces convertisseurs sontconnectés à l’extérieur de la puce. Une alternative aux convertisseurs conventionnels est leconvertisseur à capacités commutés, qui a l’avantage d’être facilement intégrable sur silicium.Toutefois, il présente des limitations à cause de la dépendance du facteur de conversion avec lenombre de condensateurs. De plus, les pertes inhérentes à la charge et à la décharge descondensateurs font diminuer son rendement. Il est donc intéressant de trouver une nouvellealternative pour concevoir un convertisseur DC/DC compact et performant afin d’obtenir un circuitélectronique complètement intégrable sur silicium.Le sujet de cette thèse répond au besoin d’une nouvelle méthode de conversion DC/DCintégrable sur silicium et à haut rendement. L’idée est d’utiliser une capacité variable mécaniquementà la place d’une inductance pour stocker l’énergie électrique transitoire. Le condensateur variable serafabriqué par des procédés de fabrication de microsystème MEMS sur silicium ce qui permet d’intégrerla totalité du convertisseur.Dans ce mémoire, nous expliquons tout d’abord le principe et le fonctionnement d’un abaisseur etd’un élévateur de tension utilisant notre nouvelle approche. Par la suite, nous présentons laconception et la fabrication d'un MEMS adapté à la conversion de tension. Finalement, nousexpliquons notre méthode de contrôle utilisant une commutation à zéro de tension. Le rendement d'unélévateur 10V-20V obtenu par simulation est de l’ordre de 88% lorsque la gestion électrique estréalisée avec des composants discrets. Ce rendement très prometteur, devrait être amélioré dans lefutur lorsque tout le système sera intégré sur silicium. / Current trends towards miniaturization of electronic circuits had led to the advent of System onChip containing different types of circuits indented to perform different functions. These sub-systemsrequire different supply voltages that are delivered from the SoC supply voltage using several DC/DCconverters. Currently, most of the electronic circuits of portable applications use conventional SMPS(switch mode power supply) DC/DC converters containing an inductor element to stock temporally theelectrical energy.In this case the converter is outside the chip since the integration of the inductor is very difficultand that resistive losses increase when the coil diameter decreases. The alternative to use switchedcapacitor converters, which can be easily integrated on silicon, presents some limitations because ofthe dependence of the required number of capacitors on the conversion ratio, and because ofswitching losses due to the charge and the discharge of the capacitors inducing a decrease of theconversion efficiency. For that reason, it is interesting to develop a new alternative that allows thefabrication of a compact and efficient DC/DC converter in order to get a completely integrated system.This thesis focuses on a novel solution based on electrostatic MEMS in order to make anintegrated DC/DC converter with high efficiency. A mechanically variable capacitor is used instead ofthe inductor element to store the transient electrical energy. The variable capacitor is fabricated byMEMS micromachining process techniques compatible with CMOS process integration.In this work, we explain the principle and the operation of a step down and a step-up converterusing our novel approach through an energetic analysis, we design a MEMS device optimized withrespect to the voltage conversion application, and we present our converter control method using azero voltage switching technique. An efficiency of almost 88% was obtained by simulation of a 10V-20V converter, when the power management circuitry was considered with discrete elements; thisefficiency is promising and could be improved when the whole system will be integrated on silicon.:

This master’s thesis deals with grid dip meter, its operating principle, characteristics and with measuring procedure. The thesis contains basic division of oscilators, its characteristics and operating principal. The master`s thesis contains complete design of grid dip meter with large-diameter measuring coil which is placed outside the device. Grip dip meter is made of SMD components on a one-sided printed wiring. Grip dip meter consist of transformer itself, that has two secondary windings as a supply for resonance meters and internal digital frequency meter. The device has analog panel gauge and BNC input for extrenal counter.

No description available.