Abstract Four high-performance circuits design techniques for embedded DRAM are proposed. First, a negative voltage generator having high efficiency is proposed to provide the negative voltage for the modified word line driver. The negative voltage generator circuits could be manufactured in n-Well CMOS process, and its operation achieve optimal output voltage. When 2.0-V supplied voltage is applied, the output voltage of -1.6-V is obtained. Even though, the supplied voltage is scaled down to 1.5-V, the output voltage can still achieve -1.05-V. In contrast, the output voltage of traditional one under 2.0-V supplied voltage is only -0.67-V. Second, a fast wordline driver suitable for PMOS pass transistor is proposed. The wordline driver improves the turned-on time by 26.8ns compared with the traditional one and raises the operating speed by 79%. Third, a new reduced clock-swing driver is proposed. Under 2.0-V supplied voltage and 100MHz operating frequency, the total power consumption of the new driver working with RCSFF is reduced by 10% than that of traditional one working with RCSFF. For the above advantage of low power, the new driver is thus more suitable for embedded DRAM applications. Fourth, a modified hierarchical read bus amplifier is proposed. The read bus amplifier is based on the new sense-amplifier. It could drive the output by full-swing voltage. It improves the sensing speed by 2.1ns. And it got the same advantage of no dc idling current as the traditional N&PMOS cross-coupled amplifier. In this thesis, finally, the performance of these circuits is also integrated and examined in an 1-Kbit embedded DRAM test circuit. The simulation RAS access time of 27.9ns is achieved under 2.0V supplied voltage and loading of 16-Mbit embedded DRAM. This indicated the above proposed circuits could be applied in the low voltage and high speed embedded DRAM.