The benefits of the continued progress in integrated circuit manufacturing have been numerous, most notably in the explosion of computing power in devices ranging from cell phones to cars. Key to this success has been strategies to identify, manage, and mitigate yield loss. One such strategy is the use of test structures to identify sources of yield loss early in the development of a new manufacturing process. However, the aggressive scaling of feature dimensions, the integration of new materials, and the increase in structural complexity in modern technologies has challenged the capabilities of conventional test structures. To help address these challenges, a new logic test chip, called the Carnegie Mellon Logic Characterization Vehicle (CM-LCV), has been developed. The CM-LCV utilizes a two- dimensional array of functional unit blocks (FUBs) that each implement an innovative functionality. Properties including fault coverage, logical and physical design features, and fault distinguishability are shown to be composable within the FUB array; that is, they exist regardless of the size and composition of the FUB array. A synthesis ow that leverages this composability to adapt the FUB array to a wide range of test chip design requirements is presented. The connection between the innovative FUB functionality and orthogonal Latin squares is identified and used to analyze the universe of possible FUB functions. Two additional variants to the FUB array are also developed: heterogenous FUB arrays utilize multiple FUB functions to improve the synthesis ow performance, while pipelined FUB arrays incorporate sequential circuit elements (e.g., ip- ops and latches) that are absent from the original combinational FUB array. In addition to the design of the CM-LCV, methods for testing it are presented. Techniques to create minimal sets of test patterns that exhaustively exercise each FUB within the FUB array are developed. Additional constraints are described for the heterogenous and pipelined FUB arrays that allow these techniques to be applied for both variant FUB arrays. Furthermore, a simple built-in self test (BIST) scheme is described and applied to a reference design, resulting in a 88.0% reduction in the number of test cycles required without loss in fault coverage. A hierarchical FUB array diagnosis methodology (HFAD) is also presented for the CM- LCV that leverages its unique properties to improve performance for multiple defects. Experiments demonstrate that this HFAD methodology is capable of perfect accuracy in 93.1% of simulations with two injected faults, an improvement on the state-of-the-art commercial diagnosis. Additionally, silicon fail data was collected from a CM-LCV manufactured using a 14nm process by an industry partner. A comparison of the diagnosis results for the 1,375 fail logs examined shows that the HFAD methodology discovers additional defects during multiple defect diagnosis that the commercial tool misses for 40 of the diagnosed fail logs. Examination of these cases shows that the additional defects found by the HFAD methodology can result in improved diagnosis confidence and more precise descriptions of the defect behavior(s). The contributions of this dissertation can thus be summarized as the description of the design, test, and diagnosis of a new logic test chip for use in yield learning during process development. This CM-LCV can be adapted to meet a wide range of test chip requirements, can be efficiently and rigorously tested, and exhibits properties that can be used to improve diagnosis outcomes. All of these claims are validated through both simulated experiments and silicon data.

Identifying common root causes of systematic defects in a short time is crucial for yield improvement. Diagnosis driven yield analysis (DDYA) such as Root cause deconvolution (RCD) is a method to estimate root cause distribution by applying statistical analysis on volume diagnosis. By fixing identified common root causes, yield can be improved. With advanced technologies, smaller feature size and more complex fabrication processes for manufacturing VLSI semiconductor devices lead to more complicated failure mechanisms. Lack of domain knowledge of such failure mechanisms makes identifying the emerging root causes more and more difficult. These root causes include but are not limited to layout pattern (certain prone to fail layout shapes) and cell internal root causes. RCD has proved to have certain degree of success in previous work, however, these root cause are not included and pose a challenge for RCD. Furthermore, complex volume diagnosis brings difficulty in investigation on RCD. To overcome the above challenges to RCD, improvement based on better understanding of the method is desired. The first part of this dissertation proposes a card game model to create controllable diagnosis data which can be used to evaluate the effectiveness of DDYA techniques. Generally, each DDYA technique could have its own potential issues, which need to be evaluated for future improvement. However, due to limitation of real diagnosis data, it is difficult to, 1. Obtain diagnosis data with sufficient diversity and 2. Isolate certain issues and evaluate them separately. With card game model given correct statistical model parameters, impact of different diagnosis scenarios on RCD are evaluated. Overfitting problem from limited sample size is alleviated by the proposed cross validation method. In the second part of this dissertation, an enhanced RCD flow based on pre-extract layout patterns is proposed to identify layout pattern root causes. Prone to fail layout patterns are crucial factors for yield loss, but they normally have enormous number of types which impact the effectiveness of RCD. Controlled experiment shows effectiveness of enhanced RCD on both layout pattern root causes and interconnect root causes after extending to layout pattern root causes. Test case from silicon data also validates the proposed flow. The last part of this dissertation addresses RCD extension to cell internal root causes. Due to limitation of domain knowledge in both diagnosis process and defect behavior, parameters of RCD model are not perfectly accurate. As RCD moves to identify cell internal root causes, such limitation become an unescapable challenge for RCD. Due to inherent characteristics of cell internal root cause, RCD including cell internal root cause faces more difficulty due to less accurate model parameters. Rather than enhancing domain knowledge, supervised learning for more accurate parameters based on training data are proposed to improve accuracy of RCD. Both controlled experiments and real silicon data shows that with parameters learned from supervised learning, accuracy of RCD with cell internal root cause are greatly improved.