For the next generation of multimedia applications such as digital video broadcasting, multimedia message service and video conference, enormous amounts of video context will be transmitted and exchanged through the wireless channel. Due to the limited communication bandwidth, how to achieve more efficient, reliable, and robust video compression is a very important issue. H.264/AVC (Advanced Video Coding) is one of the latest video coding standards, which is anticipated to be adopted in many future application systems due to its excellent compression efficiency. In this thesis, the implementation issue of the H.264 decoding algorithm on the SOC (System-On-Chip) development platform is addressed. Several key modules of H.264 decoders including color space converter, inter-interpolation, transformation rescale modules are all realized by dedicated hardware architectures. A novel low-cost fast scalable deblocking filter based on single-port memory architecture is also proposed which can support fast real-time deblocking filtering process. The entire H.264 decoder system is prototyped on the Altera SOPC platform, and the decoding result is displayed directly on the monitor. All the hardware modules are hooked on the system Avalon bus, and interact with Altera NIOS-ΒΆΒΊ processor. Through the hardware/software co-design approach, the decoding speed can be increase by a factor of 1.9.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0906105-002307 |
| Date | 06 September 2005 |
| Creators | Kuan, Yi-Sheng |
| Contributors | Shiann-Rong Kuang, Chuen-Yau Chen, Yun-Nan Chang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0906105-002307 |
| Rights | not_available, Copyright information available at source archive |
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