The operation speed of modern computer system has been upgraded from several hundred MHz to GHz. The instant current will pass to the power plane of the mother board by way of the IC pins and result in electromagnetic wave propagation between the power and ground plane, so called ¡§Ground bounce.¡¨ To prevent the ground bounce from IC operation, decoupling capacitors are used. In this thesis, an efficient numerical approach which is based on the two-dimensional (2D) finite-difference time-domain (FDTD) method and with a new recursive algorithm has been used for modeling the power/ground planes characteristics with SMT capacitors above them. By the way, we take several methods, such as Debye model, FDTD-SPICE, and telegrapher¡¦s equation, for modeling various mother board structures. Finally, we use the genetic algorithm for calculating the optimum capacitor placements to meet the expect ground bounce limitation.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0708103-122438 |
| Date | 08 July 2003 |
| Creators | Tsai, Chia-Ling |
| Contributors | Ken-Huang Lin, Tzyy-Sheng Horng, Chih-Wen Kuo, Tzong-Lin Wu, Sheng-Fu Chang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0708103-122438 |
| Rights | unrestricted, Copyright information available at source archive |
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