Two different topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of a 6-T SRAM cell using dual threshold voltage transistors and low power quenchers. We proposed a SRAM cell with dual threshold voltage transistors. The advantages of such a design is to reduce the access time and maintain data retention at the same time. Besides, the unwanted oscillation of the output data lines caused by large currents is reduced by adding two back-to-back quenchers.
The second topic is focused on the implementation of a programmable PLL-based frequency multiplier. Using the method of a phase-locked loop and a programmable divisor to implement a frequency multiplier. ¢Ï synchronous clock signal can be generated by the proposed design. It can also be used in wireless communication systems, e.g. local oscillators.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0626102-144642 |
| Date | 26 June 2002 |
| Creators | Chen, Kuo-Long |
| Contributors | Sying-Jyan Wang, Chua-Chin Wang, Chi-Feng Wu, Shen-Fu Hsiao |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0626102-144642 |
| Rights | not_available, Copyright information available at source archive |
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