Threshold logic gates are gaining more importance in recent years due to significant development in switching devices. This renewed the interest in high performance and low power circuits with threshold logic gates. Threshold Logic Gates can be implemented using both the traditional CMOS technologies and the emerging nanoelectronic technologies. In this dissertation, we have performed performance analysis on Monostable-Bistable Threshold Logic Element based, current mode, and memristor based threshold logic implementations. Existing analytical approaches that model the delay of a Monostable-Bistable Threshold Logic Element threshold logic gate cannot explore the enormous search space in the quest of weight assignments on the inputs and threshold in order to optimize the delay of the threshold logic gate. It is shown that this can be achieved by using a quantity that depends on the constants and Resonant Tunnel Diode weights. This quantity is used to form an integer linear program that optimizes the performance and ensure that each weight can tolerate a predetermined variation by an appropriate weight assignment in a threshold logic gate. The presented experimental results demonstrate the impact of the proposed method. The optimality of our solutions and the reported improvements ensure tolerance to potential manufacturing defects. Current mode is a popular CMOS-based implementation of threshold logic functions where the gate delay depends on the sensor size. A new implementation of current mode threshold functions for improved performance and switching energy is presented. An analytical method is also proposed in order to identify quickly the optimum sensor size. Experimental results on different gates with the optimum sensor size indicate that the proposed method outperforms consistently the existing implementations, and implements high performance and low power gates that have a very large number of inputs. A new dual clocked design that uses memristors in current mode logic implementation of threshold logic gates is also presented. Memristor based designs have high potential to improve performance and energy over purely CMOS-based combinational methods. The proposed designs are clocked, and outperform a recently proposed combinational method in performance as well as energy consumption. It is experimentally verified that both designs scale well in both energy consumption as well as delay.
| Identifer | oai:union.ndltd.org:siu.edu/oai:opensiuc.lib.siu.edu:dissertations-2192 |
| Date | 01 December 2015 |
| Creators | Dara, Chandra Babu |
| Publisher | OpenSIUC |
| Source Sets | Southern Illinois University Carbondale |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | Dissertations |
Page generated in 0.0021 seconds