As CMOS device dimensions are being aggressively scaled, the device characteristic must be assessed against fundamental physical limits. Nanoscale device modelling and statistical circuit analysis is needed to provide designer with ability to explore innovative new MOSFET devices as well as understanding the limits of the scaling process. This work introduces a systematic simulation methodology to investigate the impact of intrinsic parameter fluctuation for a novel Ultra-Thin-Body (UTB) Silicon-on-Insulator (SOI) transistor on the corresponding device and circuits. It provides essential link between physical device-level numerical simulation and circuit-level simulation. A systematic analysis of the effects of random discrete dopants, body thickness variations and line edge roughness on a well scaled 10 nm, 7.5 nm and 5 nm channel length UTB-SOI MOSFET is performed. To fully realise the performance benefits of UTB-SOI based SRAM cells a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuations information into the compact model is developed. The impact of intrinsic parameter fluctuations on the stability and performance of 6T SRAM has been investigated. A comparison with the behaviour of a 6T SRAM based on a conventional 35 nm MOSFET is also presented.
| Identifer | oai:union.ndltd.org:bl.uk/oai:ethos.bl.uk:433197 |
| Date | January 2006 |
| Creators | Samsudin, Khairulmizam |
| Publisher | University of Glasgow |
| Source Sets | Ethos UK |
| Detected Language | English |
| Type | Electronic Thesis or Dissertation |
| Source | http://theses.gla.ac.uk/5417/ |
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