This thesis presents the design and experimental results of a low-power pipeline ADC that applies front-end capacitor-sharing. The ADC operates at 20 MS/s, resolves 1.5 bits/stage, and is implemented in IBM 0.13um technology. The purpose of the technique is to reduce power consumption in the front-end S/H. This work is a proof-of-concept and it concentrates on the front-end design. A comparison is conducted between a capacitor-sharing ADC and a regular ADC and as a result, the technique reduces the power consumption in the front-end S/H by 39%. At an input frequency of 9.53 MHz and a sampling rate of 20 MS/s, the fabricated capacitor-sharing ADC consumes 4.7 mW at 1.2 V, and it achieves an ENOB of 8.5 bits and a FOM of 0.68 pJ/step. It has an ENOB as high as 8.67 bits at 0.4 MS/s and a FOM as low as 0.6 pJ/step when sub-sampling at 20 MS/s.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OTU.1807/32294 |
| Date | 26 March 2012 |
| Creators | Zhang, Guangzhao |
| Contributors | Johns, David A. |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | en_ca |
| Detected Language | English |
| Type | Thesis |
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