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1	Digital-To-Analog Converter for FSK Salim J, Athfal January 2007 (has links) <p>This thesis is one part of a overall task of designing a module for frequency shift keying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has a Direct Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differential current signals are directly fed to a RF (Radio Frequency) unit that generates the UWB RF signal.</p><p>The focus of this thesis is on DAC while the DDS is developed in VHDL as another thesis work. This thesis demonstrates a low-power, ultra wide band 10 bit DAC with an update frequency of 24 MSPS(Mega Samples Per Second). The DAC uses a L-fold linear interpolation architecture. It includes a 16-tap voltage controlled delay line and a 10 bit binary-weighted DAC with a time interleaved structure. The linear interpolation technique improves the attenuation of mirror components and also reduces the glitch. This helps to relax the analog filter requirements and sometimes an off chip capacitor is enough as low pass filter. The attenuation of image components is doubled in decibels(dB) compared with that of conventional DAC.</p><p>In this work various DAC architectures are studied. The current-steering DAC is chosen due to its high speed and high resolution. A binary weighted architecture is chosen to reduce the digital circuits. This helped in reducing the power consumption. The design and simulation is done with help of Cadence. The layout is done in Cadence Virtuoso and the DDS is integrated with the DAC. The chip is to be manufactured in 130 nm CMOS process.</p> DAC FSK 10-bit layout 130 nm Digital-To-Analog CMOS Common centroid Electronics Elektronik
2	Digital-To-Analog Converter for FSK Salim J, Athfal January 2007 (has links) This thesis is one part of a overall task of designing a module for frequency shift keying (FSK) to be used in an Ultra Wide Band (UWB) system. The FSK system has a Direct Digital Synthesizer (DDS) and Digital-to-Analog (DAC). The DACs differential current signals are directly fed to a RF (Radio Frequency) unit that generates the UWB RF signal. The focus of this thesis is on DAC while the DDS is developed in VHDL as another thesis work. This thesis demonstrates a low-power, ultra wide band 10 bit DAC with an update frequency of 24 MSPS(Mega Samples Per Second). The DAC uses a L-fold linear interpolation architecture. It includes a 16-tap voltage controlled delay line and a 10 bit binary-weighted DAC with a time interleaved structure. The linear interpolation technique improves the attenuation of mirror components and also reduces the glitch. This helps to relax the analog filter requirements and sometimes an off chip capacitor is enough as low pass filter. The attenuation of image components is doubled in decibels(dB) compared with that of conventional DAC. In this work various DAC architectures are studied. The current-steering DAC is chosen due to its high speed and high resolution. A binary weighted architecture is chosen to reduce the digital circuits. This helped in reducing the power consumption. The design and simulation is done with help of Cadence. The layout is done in Cadence Virtuoso and the DDS is integrated with the DAC. The chip is to be manufactured in 130 nm CMOS process. DAC FSK 10-bit layout 130 nm Digital-To-Analog CMOS Common centroid Electronics Elektronik
3	A Low-power Pipeline ADC with Front-end Capacitor-sharing Zhang, Guangzhao 26 March 2012 (has links) This thesis presents the design and experimental results of a low-power pipeline ADC that applies front-end capacitor-sharing. The ADC operates at 20 MS/s, resolves 1.5 bits/stage, and is implemented in IBM 0.13um technology. The purpose of the technique is to reduce power consumption in the front-end S/H. This work is a proof-of-concept and it concentrates on the front-end design. A comparison is conducted between a capacitor-sharing ADC and a regular ADC and as a result, the technique reduces the power consumption in the front-end S/H by 39%. At an input frequency of 9.53 MHz and a sampling rate of 20 MS/s, the fabricated capacitor-sharing ADC consumes 4.7 mW at 1.2 V, and it achieves an ENOB of 8.5 bits and a FOM of 0.68 pJ/step. It has an ENOB as high as 8.67 bits at 0.4 MS/s and a FOM as low as 0.6 pJ/step when sub-sampling at 20 MS/s. pipeline ADC 20 MS/s 10-bit front-end capacitor-sharing 0544
4	A Low-power Pipeline ADC with Front-end Capacitor-sharing Zhang, Guangzhao 26 March 2012 (has links) This thesis presents the design and experimental results of a low-power pipeline ADC that applies front-end capacitor-sharing. The ADC operates at 20 MS/s, resolves 1.5 bits/stage, and is implemented in IBM 0.13um technology. The purpose of the technique is to reduce power consumption in the front-end S/H. This work is a proof-of-concept and it concentrates on the front-end design. A comparison is conducted between a capacitor-sharing ADC and a regular ADC and as a result, the technique reduces the power consumption in the front-end S/H by 39%. At an input frequency of 9.53 MHz and a sampling rate of 20 MS/s, the fabricated capacitor-sharing ADC consumes 4.7 mW at 1.2 V, and it achieves an ENOB of 8.5 bits and a FOM of 0.68 pJ/step. It has an ENOB as high as 8.67 bits at 0.4 MS/s and a FOM as low as 0.6 pJ/step when sub-sampling at 20 MS/s. pipeline ADC 20 MS/s 10-bit front-end capacitor-sharing 0544
5	A novel 10-bit hybrid ADC using flash and delay line architectures Dutt, Samir 11 July 2011 (has links) This thesis describes the architecture and implementation of a novel 10-bit hybrid Analog to Digital Converter using Flash and Delay Line concepts. Flash ADCs employ power hungry comparators which increase the overall power consumption of a high resolution ADC. High resolution flash also requires precision analog circuit design. Delay line ADCs are based on digital circuits and operate at low power. Both Flash based ADCs and delay line based ADCs can be used to get a fast analog to digital conversion, but with limited resolution. These two approaches are combined to achieve a 10-bit resolution (4 bits using Flash and 6 bits using delay line) without compromising on speed and maintaining low power operation. Low resolution of Flash also helps in reducing the analog circuit design complexity of the voltage comparators. The ADC was capable of running at 100M samples/s, with an ENOB of 8.82 bits, consuming 8.59mW at 1.8V. / text Flash ADC Vernier delay line ADC Low power ADC Integrated circuits and systems
6	A 10-Bit Dual Plate Sampling Capacitive DAC with Auto-Zero On-Chip Reference Voltage Generation Gaddam, Ravi Shankar 01 November 2012 (has links) No description available. Electrical Engineering Engineering Dual plate sampling switched-capacitor circuit digital-to-analog converter auto-zero technique DAC display driver 10-bit reference generator
7	Design of a Low Power, High Performance Track-and-Hold Circuit in a 0.18µm CMOS Technology / Design av en lågeffekts högprestanda track-and-hold krets i en 0.18µm CMOS teknologi. Säll, Erik January 2002 (has links) This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter. A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type. The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase. The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins. Electronics track-and-hold CMOS 0.18 low power high performance 10-bit folded cascode switch theory correlated double sampling CDS fully differential gain boosting regulated cascode transmission gate transmission gate switch clock generator clock driver bias bias circuit amplifier design switch design common mode feedback CMFB 80MSPS 80MS/s Elektronik Electronics Elektronik
8	Design of a Low Power, High Performance Track-and-Hold Circuit in a 0.18µm CMOS Technology / Design av en lågeffekts högprestanda track-and-hold krets i en 0.18µm CMOS teknologi. Säll, Erik January 2002 (has links) <p>This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter. </p><p>A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type. </p><p>The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase. </p><p>The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins.</p> Electronics track-and-hold CMOS 0.18 low power high performance 10-bit folded cascode switch theory correlated double sampling CDS fully differential gain boosting regulated cascode transmission gate transmission gate switch clock generator clock driver bias bias circuit amplifier design switch design common mode feedback CMFB 80MSPS 80MS/s Elektronik Electronics Elektronik

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