Las actuales arquitecturas de m�ltiples n�cleos como los chip multiprocesadores (CMP) y soluciones multiprocesador para sistemas dentro del chip (MPSoCs) han adoptado a las redes dentro del chip (NoC) como elemento -ptimo para la inter-conexi-n de los diversos elementos de dichos sistemas. En este sentido, fabricantes de CMPs y MPSoCs han adoptado NoCs sencillas, generalmente con una topolog'a en malla o anillo, ya que son suficientes para satisfacer las necesidades de los sistemas actuales. Sin embargo a medida que los requerimientos del sistema -- baja latencia y alto rendimiento -- se hacen m�s exigentes, estas redes tan simples dejan de ser una soluci-n real. As', la comunidad investigadora ha propuesto y analizado NoCs m�s complejas. No obstante, estas soluciones son m�s dif'ciles de implementar -- especialmente los enlaces largos -- haciendo que este tipo de topolog'as complejas sean demasiado costosas o incluso inviables. En esta tesis, presentamos una metodolog'a de dise-o que minimiza la p�rdida de prestaciones de la red debido a su implementaci-n real. Los principales problemas que se encuentran al implementar una NoC son los conmutadores y los enlaces largos. En esta tesis, el conmutador se ha hecho modular, es decir, formado como uni-n de m-dulos m�s peque-os. En nuestro caso, los m-dulos son id�nticos, donde cada m-dulo es capaz de arbitrar, conmutar, y almacenar los mensajes que le llegan. Posteriormente, flexibilizamos la colocaci-n de estos m-dulos en el chip, permitiendo que m-dulos de un mismo conmutador est�n distribuidos por el chip. Esta metodolog'a de dise-o la hemos aplicado a diferentes escenarios. Primeramente, hemos introducido nuestro conmutador modular en NoCs con topolog'as conocidas como la malla 2D. Los resultados muestran como la modularidad y la distribuci-n del conmutador reducen la latencia y el consumo de potencia de la red. En segundo lugar, hemos utilizado nuestra metodolog'a de dise-o para implementar un crossbar distribuid / Roca Pérez, A. (2012). Floorplan-Aware High Performance NoC Design [Tesis doctoral]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/17844

Thesis (PhD (Electrical and Electronic Engineering)--University of Stellenbosch, 2007. / ENGLISH ABSTRACT: A monostatic baseband radar is required with the capability of detecting close range targets that appear at distances comparable to the system’s resolution, without compromising the radar’s maximum range. The application in borehole radar imposes further constraints associated with the physical limitations and variable electromagnetic environment of different borehole diameters and conditions. This dissertation discusses the complete design process of the analog section of a monostatic radar that successfully addresses these issues. The proposed transceiver employs a series duplexing arrangement consisting of an antenna, transmitter, receiver and an isolation switch. An exponentially decaying tail is observed in the current flowing on a borehole radar antenna when excited by pulse waveforms. The characteristics of this tail depend strongly on the borehole environment. A measurement technique is developed that accurately quantifies this exponential decay by digitizing a logarithmic representation of the antenna current while it is operating in various boreholes. Transmitters are then designed to drive these antennas with waveforms that prevent the formation of current tails. This is achieved through the use of pole-zero networks or alternatively by generating certain asymmetric, bipolar waveforms. The transmitters are simultaneously designed to have an output impedance approximating a short circuit after the transient is generated. In the series configuration proposed here, the duplexing of the antenna between transmitter and receiver is then reduced to simply isolating the receiver during transmit-mode. The switch responsible for this isolation disconnects the receiver and presents a short circuit between antenna and transmitter during transmit-mode, while connecting the receiver terminals between the antenna and the short circuited transmitter terminals in receive-mode. The required close-in performance of the transceiver dictates that the transition between these two states of the isolation switch occur in a time similar to the duration of the transmitter waveform. The switching artefacts generated by the switch are consequently similar to the radar data signal. The isolation switch employs an innovative configuration (using both transistors and diodes) which accepts a single control signal and causes the switching artefacts to be generated as a common mode signal, while a differential path is created for the radar data signal which is being switched. This leads to effective suppression of the switching signal in the signal passed to the receiver. Dissipative filtering is advocated as a fundamental design principle for high fidelity receivers and it is shown how it can be applied by using constant impedance equalizers and diplexers as basic building blocks. This principle is used as the basis for the design of this transceiver's receivers, which incorporate both standard gain blocks and operational amplifiers. A complete borehole radar system, based on the transceiver developed here, was built and tested; resulting in the first known practical monostatic borehole radar system. Data obtained in field trials are presented and suggest that the monostatic system compares well with current state of the art bi-static systems. / AFRIKAANSE OPSOMMING: Die behoefte is geïdentifiseer vir 'n monostatiese basisbandradar wat oor die vermoë beskik om nabygeleë teikens op 'n afstand soortgelyk aan die resolusie van die stelsel waar te neem, sonder om die maksimum bereik van die stelsel in te kort. Die toepassing daarvan in 'n boorgatradarstelsel lei tot verdere vereistes vanweë die fisiese beperkings en veranderende elektromagnetiese omgewing van boorgate met verskillende deursnitte en toestande. Hierdie proefskrif is gemoeid met die volledige ontwerpsprosedure van die analoog gedeelte van 'n monostatiese radar wat al hierdie kwessies aanspreek. 'n Serie verbinding van antenne, sender, ontvanger en isolasieskakelaar word ingespan vir hierdie ontwerp. Eksponensieel wegsterwende stertjies word waargeneem in die antennestroom van 'n boorgatradarantenne wanneer dit aangedryf word deur puls golfvorms. 'n Meettegniek word ontwikkel wat hierdie eksponensiële verslapping noukeurig kan monitor deur 'n logaritmiese voorstelling van die antennastroom te versyfer terwyl dit ontplooi word in verskillende boorgate. Senders word dan ontwikkel om hierdie antennes aan te dryf met golfvorms wat juis die vorming van hierdie stertjies voorkom. Dit word bewerkstellig deur die gebruik van pool-zero netwerke of andersins deur die opwek van sekere asimmetriese, bipolêre golfvorms. Die senders se uittree-impedansies moet egter terselfdertyd ontwerp word om 'n kortsluiting te benader sodra die oorgang klaar opgewek is. Met die serie verbinding wat hier gebruik word, raak die vereiste tyddeling van die antenna tussen die sender en ontvanger dan bloot 'n geval van ontvanger-isolasie gedurende uitsaai-modus. Die skakelaar wat verantwoordelik is vir hierdie isolasie ontkoppel die ontvanger en vertoon soos 'n kortsluiting tussen sender en antenne tydens uitsaai-modus, maar verbind weer die terminale van die ontvanger tussen die antenne en kortgeslote senderterminale tydens ontvang-modus. Die vereiste kortafstand vermoë van die stelsel veroorsaak dat die tysduur van die oorgang tussen hierdie twee modusse soortgelyk is aan dié van die sender golfvorm en enige skakelverskynsels wat opgewek word deur die skakelaar is gevolglik soortgelyk aan die radardatasein self. Die isolasieskakelaar gebruik egter 'n innoverende konfigurasie (met transistors sowel as diodes) wat funksioneer met 'n enkele beheersein en die skakelverskynsels as gemene modus seine opwek, terwyl 'n differensiële seinpad geskep word vir die radardatasein wat geskakel word. Die skakelseine word gevolglik effektief onderdruk in die sein wat oorgedra word aan die ontvanger. Die gebruik van verkwistende filters word voorgestel as 'n fundamentele ontwerpsbeginsel vir hoëtrou ontvangers en daar word getoon hoe dit toegepas kan word met konstante impedansie vereffeningsbane en dipleksers. Hierdie beginsel is dan ook gebruik as basis vir die ontwerp van hierdie stelsel se ontvangers, wat gebruik maak van beide standard aanwinsblokke sowel as operasionel versterkers. 'n Volledige boorgatradarstelsel, gebaseer op die stelsel wat hier ontwikkel is, is gebou en getoets. Die gevolg is die eerste bekende, praktiese monostatiese boorgatradarstelsel. Data wat hiermee verwerf is word aangebied en dui daarop dat die monostatiese stelsel baie goed opweeg teen huidige bi-statiese stelsels.

RF switches are an essential building block in numerous applications, including tactical radar systems, satellite communications, global positioning systems (GPS), automotive radars, wireless communications, radio astronomy, radar transceivers, and various instrumentation systems. For many of these applications the circuits have to operate reliably under extreme operating conditions, including conditions outside the domain of commercial military specifications. The objective of this thesis is to present the design procedure, simulation, and measurement results for Radio Frequency (RF) switches in 130 nm Silicon Germanium (SiGe) BiCMOS process technology. The novelty of this work lies in the proposed new topology of an ultrahigh-isolation single-pole, single-throw (SPST) and a single pole, four-throw (SP4T) nMOS based switch for multiband microwave radar systems. The analysis of cryogenic temperature effects on these circuits and devices are discussed in this work. The results shows that several key-figures-of-merits of a switch, like insertion loss, isolation, and power handling capability (P1dB) improve at cryogenic temperatures. These results are important for several applications, including space-based extreme environment application where FET based circuits would need to operate reliably across a wide-range of temperature.

This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter. A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type. The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase. The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins.

<p>This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter. </p><p>A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type. </p><p>The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase. </p><p>The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins.</p>