Global ETD Search

1	Optimization and Modeling of FPGA Circuitry in Advanced Process Technology Chiasson, Charles 21 November 2013 (has links) We develop a new fully-automated transistor sizing tool for FPGAs that features area, delay and wire load modeling enhancements over prior work to improve its accuracy in advanced process nodes. We then use this tool to investigate a number of FPGA circuit design related questions in a 22nm process. We find that building FPGAs out of transmission gates instead of the currently dominant pass-transistors, whose performance and reliability are degrading with technology scaling, yields FPGAs that are 15% larger but are 10-25% faster depending on the allowable level of "gate boosting''. We also show that transmission gate FPGAs with a separate power supply for their gate terminal enable a low-voltage FPGA with 50% less power and good delay. Finally, we show that, at a possible cost in routability, restricting the portion of a routing channel that can be accessed by a logic block input can improve delay by 17%. FPGA circuit design advanced process technology optimization modeling transistor sizing transmission gate FPGA 0544
2	Optimization and Modeling of FPGA Circuitry in Advanced Process Technology Chiasson, Charles 21 November 2013 (has links) We develop a new fully-automated transistor sizing tool for FPGAs that features area, delay and wire load modeling enhancements over prior work to improve its accuracy in advanced process nodes. We then use this tool to investigate a number of FPGA circuit design related questions in a 22nm process. We find that building FPGAs out of transmission gates instead of the currently dominant pass-transistors, whose performance and reliability are degrading with technology scaling, yields FPGAs that are 15% larger but are 10-25% faster depending on the allowable level of "gate boosting''. We also show that transmission gate FPGAs with a separate power supply for their gate terminal enable a low-voltage FPGA with 50% less power and good delay. Finally, we show that, at a possible cost in routability, restricting the portion of a routing channel that can be accessed by a logic block input can improve delay by 17%. FPGA circuit design advanced process technology optimization modeling transistor sizing transmission gate FPGA 0544
3	Sampling Ocsilloscope On-Chip Forsgren, Niklas January 2003 (has links) Signal-integrity degradation from such factors as supply and substrate noise and cross talk between interconnects restricts the performance advances in Very Large Scale Integration (VLSI). To avoid this and to keep the signal-integrity, accurate measurements of the on-chip signal must be performed to get an insight in how the physical phenomenon affects the signals. High-speed digital signals can be taken off chip, through buffers that add delay. Propagating a signal through buffers restores the signal, which can be good if only information is wanted. But if the waveform is of importance, or if an analog signal should be measured the restoration is unwanted. Analog buffers can be used but they are limited to some hundred MHz. Even if the high-speed signal is taken off chip, the bandwidth of on-chip signals is getting very high, making the use of an external oscilloscope impossible for reliable measurement. Therefore other alternatives must be used. In this work, an on-chip measuring circuit is designed, which makes use of the principle of a sampling oscilloscope. Only one sample is taken each period, resulting in an output frequency much lower than the input frequency. A slower signal is easier to take off-chip and it can easily be processed with an ordinary oscilloscope. Electronics sampling high-speed sampling subsampling sampling oscilloscope on-chip source follower common source sampling switch transmission gate sample and hold track and hold MOS transistor Elektronik Electronics Elektronik
4	Sampling Ocsilloscope On-Chip Forsgren, Niklas January 2003 (has links) <p>Signal-integrity degradation from such factors as supply and substrate noise and cross talk between interconnects restricts the performance advances in Very Large Scale Integration (VLSI). To avoid this and to keep the signal-integrity, accurate measurements of the on-chip signal must be performed to get an insight in how the physical phenomenon affects the signals. </p><p>High-speed digital signals can be taken off chip, through buffers that add delay. Propagating a signal through buffers restores the signal, which can be good if only information is wanted. But if the waveform is of importance, or if an analog signal should be measured the restoration is unwanted. Analog buffers can be used but they are limited to some hundred MHz. Even if the high-speed signal is taken off chip, the bandwidth of on-chip signals is getting very high, making the use of an external oscilloscope impossible for reliable measurement. Therefore other alternatives must be used. </p><p>In this work, an on-chip measuring circuit is designed, which makes use of the principle of a sampling oscilloscope. Only one sample is taken each period, resulting in an output frequency much lower than the input frequency. A slower signal is easier to take off-chip and it can easily be processed with an ordinary oscilloscope.</p> Electronics sampling high-speed sampling subsampling sampling oscilloscope on-chip source follower common source sampling switch transmission gate sample and hold track and hold MOS transistor Elektronik Electronics Elektronik
5	Design and Simulation of a Temperature-Insensitive Rail-to-Rail Comparator for Analog-to-Digital Converter Application Kollarits, Matthew David 18 August 2010 (has links) No description available. Electrical Engineering Comparator ADC Analog-to-Digital Converter ZTC Zero-Temperature Coefficient Rail-to-Rail Complementary Folded Cascode Folded Cascode Transmission Gate SOI Silicon-on-Insulator
6	Design of a Low Power, High Performance Track-and-Hold Circuit in a 0.18µm CMOS Technology / Design av en lågeffekts högprestanda track-and-hold krets i en 0.18µm CMOS teknologi. Säll, Erik January 2002 (has links) This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter. A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type. The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase. The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins. Electronics track-and-hold CMOS 0.18 low power high performance 10-bit folded cascode switch theory correlated double sampling CDS fully differential gain boosting regulated cascode transmission gate transmission gate switch clock generator clock driver bias bias circuit amplifier design switch design common mode feedback CMFB 80MSPS 80MS/s Elektronik Electronics Elektronik
7	Design of a Low Power, High Performance Track-and-Hold Circuit in a 0.18µm CMOS Technology / Design av en lågeffekts högprestanda track-and-hold krets i en 0.18µm CMOS teknologi. Säll, Erik January 2002 (has links) <p>This master thesis describes the design of a track-and-hold (T&H) circuit with 10bit resolution, 80MS/s and 30MHz bandwidth. It is designed in a 0.18µm CMOS process with a supply voltage of 1.8 Volt. The circuit is supposed to work together with a 10bit pipelined analog to digital converter. </p><p>A switched capacitor topology is used for the T&H circuit and the amplifier is a folded cascode OTA with regulated cascode. The switches used are of transmission gate type. </p><p>The thesis presents the design decisions, design phase and the theory needed to understand the design decisions and the considerations in the design phase. </p><p>The results are based on circuit level SPICE simulations in Cadence with foundry provided BSIM3 transistor models. They show that the circuit has 10bit resolution and 7.6mW power consumption, for the worst-case frequency of 30MHz. The requirements on the dynamic performance are all fulfilled, most of them with large margins.</p> Electronics track-and-hold CMOS 0.18 low power high performance 10-bit folded cascode switch theory correlated double sampling CDS fully differential gain boosting regulated cascode transmission gate transmission gate switch clock generator clock driver bias bias circuit amplifier design switch design common mode feedback CMFB 80MSPS 80MS/s Elektronik Electronics Elektronik
8	High Speed On-Chip Measurment Circuit / Inbyggd krets för höghastighetsmätning på chip Stridfelt, Arvid January 2005 (has links) <p>This master thesis describes a design exploration of a circuit capable of measuring high speed signals without adding significant capacitive load to the measuring node. </p><p>It is designed in a 0.13 CMOS process with a supply voltage of 1.2 Volt. The circuit is a master and slave, track-and-hold architecture incorporated with a capacitive voltage divider and a NMOS source follower as input buffer to protect the measuring node and increase the input voltage range. </p><p>This thesis presents the implementation process and the theory needed to understand the design decisions and consideration throughout the design. The results are based on transistor level simulations performed in Cadence Spectre. </p><p>The results show that it is possible to observe the analog behaviour of a high speed signal by down converting it to a lower frequency that can be brought off-chip. The trade off between capacitive load added to the measuring node and input bandwidth of the measurment circuit is also presented.</p> Electronics CMOS 0.13 sampling periodic sampling digital oscilloscope time equivalent sampling track and hold master and slave sampling clock generator voltagedivider source follower sampling switch transmission gate RLC-line Elektronik Electronics Elektronik
9	High Speed On-Chip Measurment Circuit / Inbyggd krets för höghastighetsmätning på chip Stridfelt, Arvid January 2005 (has links) This master thesis describes a design exploration of a circuit capable of measuring high speed signals without adding significant capacitive load to the measuring node. It is designed in a 0.13 CMOS process with a supply voltage of 1.2 Volt. The circuit is a master and slave, track-and-hold architecture incorporated with a capacitive voltage divider and a NMOS source follower as input buffer to protect the measuring node and increase the input voltage range. This thesis presents the implementation process and the theory needed to understand the design decisions and consideration throughout the design. The results are based on transistor level simulations performed in Cadence Spectre. The results show that it is possible to observe the analog behaviour of a high speed signal by down converting it to a lower frequency that can be brought off-chip. The trade off between capacitive load added to the measuring node and input bandwidth of the measurment circuit is also presented. Electronics CMOS 0.13 sampling periodic sampling digital oscilloscope time equivalent sampling track and hold master and slave sampling clock generator voltagedivider source follower sampling switch transmission gate RLC-line Elektronik Electronics Elektronik
10	Towards No-Penalty Control Hazard Handling in RISC architecture microcontrollers LINKNATH SURYA BALASUBRAMANIAN (8781929) 03 September 2024 (has links) <p dir="ltr">Achieving higher throughput is one of the most important requirements of a modern microcontroller. It is therefore not affordable for it to waste a considerable number of clock cycles in branch mispredictions. This paper proposes a hardware mechanism that makes microcontrollers forgo branch predictors, thereby removing branch mispredictions. The scope of this work is limited to low cost microcontroller cores that are applied in embedded systems. The proposed technique is implemented as five different modules which work together to forward required operands, resolve branches without prediction, and calculate the next instruction's address in the first stage of an in-order five stage pipelined micro-architecture. Since the address of successive instruction to a control transfer instruction is calculated in the first stage of pipeline, branch prediction is no longer necessary, thereby eliminating the clock cycle penalties occurred when using a branch predictor. The designed architecture was able to successfully calculate the address of next correct instruction and fetch it without any wastage of clock cycles except in cases where control transfer instructions are in true dependence with their immediate previous instructions. Further, we synthesized the proposed design with 7nm FinFET process and compared its latency with other designs to make sure that the microcontroller's operating frequency is not degraded by using this design. The critical path latency of instruction fetch stage integrated with the proposed architecture is 307 ps excluding the instruction cache access time.</p> Circuits and systems Electrical circuits and systems Digital processor architectures Microelectronics variable reference voltage degraded switches transmission gate in-memory computing mispredictions microcontroller branch predictors control transfer instructions

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