Transistor aging through negative bias temperature instability (NBTI) has become a major lifetime constraint in VLSI circuits. We propose a technique that uses antifuses to widen PMOS transistors later in a circuit?s life cycle to combat aging. Using HSPICE and 70nm BPTM process numbers, we simulated the technique on four circuits (a ring oscillator, a fan-out four circuit, an ISCAS c432 and c2670). Over the lifetime of the circuit, our simulations predict a 8.89% and a 13% improvement in power in the c432 and c2670 circuits respectively when compared to similarly performing traditional circuits.

Field-programmable gate arrays (FPGAs) have enjoyed increasing use due to their low non-recurring engineering (NRE) costs and their straightforward implementation process. However, it is recognized that they have higher per unit costs, poorer performance and increased power consumption compared to custom alternatives, such as application specific integrated circuits (ASICs). This thesis investigates the extent of this gap and it examines the trade-offs that can be made to narrow it. The gap between 90 nm FPGAs and ASICs was measured for many benchmark circuits. For circuits that only make use of general-purpose combinational logic and flipflops, the FPGA-based implementation requires 35 times more area on average than an equivalent ASIC. Modern FPGAs also contain "hard" specific-purpose circuits such as multipliers and memories and these blocks are found to narrow the average gap to 18 for our benchmarks or, potentially, as low as 4.7 when the hard blocks are heavily used. The FPGA was found to be on average between 3.4 and 4.6 times slower than an ASIC and this gap was not influenced significantly by hard memories and multipliers. The dynamic power consumption is approximately 14 times greater on average on the FPGA than on the ASIC but hard blocks showed promise for reducing this gap. This is one of the most comprehensive analyses of the gap performed to date. The thesis then focuses on exploring the area and delay trade-offs possible through architecture, circuit structure and transistor sizing. These trade-offs can be used to selectively narrow the FPGA to ASIC gap but past explorations have been limited in their scope as transistor sizing was typically performed manually. To address this issue, an automated transistor sizing tool for FPGAs was developed. For a range of FPGA architectures, this tool can produce designs optimized for various design objectives and the quality of these designs is comparable to past manual designs. With this tool, the trade-off possibilities of varying both architecture and transistor-sizing were explored and it was found that there is a wide range of useful trade-offs between area and delay. This range of 2.1 X in delay and 2.0 X in area is larger than was observed in past pure architecture studies. It was found that lookup table (LUT) size was the most useful architectural parameter for enabling these trade-offs.

We develop a new fully-automated transistor sizing tool for FPGAs that features area, delay and wire load modeling enhancements over prior work to improve its accuracy in advanced process nodes. We then use this tool to investigate a number of FPGA circuit design related questions in a 22nm process. We find that building FPGAs out of transmission gates instead of the currently dominant pass-transistors, whose performance and reliability are degrading with technology scaling, yields FPGAs that are 15% larger but are 10-25% faster depending on the allowable level of "gate boosting''. We also show that transmission gate FPGAs with a separate power supply for their gate terminal enable a low-voltage FPGA with 50% less power and good delay. Finally, we show that, at a possible cost in routability, restricting the portion of a routing channel that can be accessed by a logic block input can improve delay by 17%.

We develop a new fully-automated transistor sizing tool for FPGAs that features area, delay and wire load modeling enhancements over prior work to improve its accuracy in advanced process nodes. We then use this tool to investigate a number of FPGA circuit design related questions in a 22nm process. We find that building FPGAs out of transmission gates instead of the currently dominant pass-transistors, whose performance and reliability are degrading with technology scaling, yields FPGAs that are 15% larger but are 10-25% faster depending on the allowable level of "gate boosting''. We also show that transmission gate FPGAs with a separate power supply for their gate terminal enable a low-voltage FPGA with 50% less power and good delay. Finally, we show that, at a possible cost in routability, restricting the portion of a routing channel that can be accessed by a logic block input can improve delay by 17%.

Field-programmable gate arrays (FPGAs) have enjoyed increasing use due to their low non-recurring engineering (NRE) costs and their straightforward implementation process. However, it is recognized that they have higher per unit costs, poorer performance and increased power consumption compared to custom alternatives, such as application specific integrated circuits (ASICs). This thesis investigates the extent of this gap and it examines the trade-offs that can be made to narrow it. The gap between 90 nm FPGAs and ASICs was measured for many benchmark circuits. For circuits that only make use of general-purpose combinational logic and flipflops, the FPGA-based implementation requires 35 times more area on average than an equivalent ASIC. Modern FPGAs also contain "hard" specific-purpose circuits such as multipliers and memories and these blocks are found to narrow the average gap to 18 for our benchmarks or, potentially, as low as 4.7 when the hard blocks are heavily used. The FPGA was found to be on average between 3.4 and 4.6 times slower than an ASIC and this gap was not influenced significantly by hard memories and multipliers. The dynamic power consumption is approximately 14 times greater on average on the FPGA than on the ASIC but hard blocks showed promise for reducing this gap. This is one of the most comprehensive analyses of the gap performed to date. The thesis then focuses on exploring the area and delay trade-offs possible through architecture, circuit structure and transistor sizing. These trade-offs can be used to selectively narrow the FPGA to ASIC gap but past explorations have been limited in their scope as transistor sizing was typically performed manually. To address this issue, an automated transistor sizing tool for FPGAs was developed. For a range of FPGA architectures, this tool can produce designs optimized for various design objectives and the quality of these designs is comparable to past manual designs. With this tool, the trade-off possibilities of varying both architecture and transistor-sizing were explored and it was found that there is a wide range of useful trade-offs between area and delay. This range of 2.1 X in delay and 2.0 X in area is larger than was observed in past pure architecture studies. It was found that lookup table (LUT) size was the most useful architectural parameter for enabling these trade-offs.

Este trabalho propõe um método de otimização de atraso, através de dimensionamento de transistores, o qual faz parte de um fluxo automático de síntese física de circuitos combinacionais em tecnologia CMOS estática. Este fluxo de síntese física é independente de biblioteca de células, sendo capaz de realizar, sob demanda, a geração do leiaute a partir de um netlist de transistores. O método de otimização proposto faz com que este fluxo de síntese física seja capaz de realizar a geração do leiaute orientado pelas restrições de atraso, garantindo a operação do circuito na freqüência especificada pelo projetista. Este trabalho inclui também uma pesquisa sobre os principais métodos de verificação e otimização de atraso, principalmente aqueles que podem ser aplicados quando a etapa de síntese física chega ao nível de transistores. Um método de análise de timing funcional é utilizado para identificar o atraso e o caminho críticos e, com isso, guiar o método de otimização proposto. Desta forma, não existe desperdício de esforço e desempenho para reduzir o atraso de caminhos que não contribuem efetivamente para determinar a freqüência do circuito. O método proposto neste trabalho explora as possibilidades oferecidas por ser independente de biblioteca de células, mas impõe restrições aos circuitos otimizados para reduzir o impacto do dimensionamento nas etapas de geração de leiaute. O desenvolvimento de um método incremental de seleção de caminhos críticos reduziu consideravelmente o tempo de processamento sem comprometer a qualidade dos resultados. Ainda, a realização de um método seletivo de dimensionamento de transistores, possibilitado pela adaptação de um modelo de atraso pino-a-pino, permitiu reduzir significativamente o acréscimo de área decorrente da otimização e aumentou a precisão das estimativas de atraso. / This work proposes a transistor sizing-based delay optimization method especially tailored for an automatic physical synthesis flow of static CMOS combinational circuits. Such physical synthesis flow is a library-free approach which is able to perform the layout generation using a transistor netlist level description of the circuit. The integration of the proposed optimization method to the automatic physical synthesis renders possible a timing-driven layout generation flow. This work also includes a research of the major delay verification and optimization methods, mainly those that can be applied during the physical synthesis step at the transistor level. A functional timing analysis method is used to identify the critical delay and the critical paths and thus drive the proposed optimization method. Hence, there is no waste of effort to optimize paths which are not responsible for the delay of the circuit. The optimization method proposed in this work explores the advantages provided by a library-free synthesis flow and imposes restrictions to the optimized circuits in order to minimize the impact of the transistor sizing in the layout generation steps. The development of a method for incremental critical path selection reduces the CPU time consumed by the delay optimization step. A pin-to-pin gate delay model was adapted to perform a selective transistor sizing, resulting in a significantly reduction of the area overhead.

Este trabalho propõe um método de otimização de atraso, através de dimensionamento de transistores, o qual faz parte de um fluxo automático de síntese física de circuitos combinacionais em tecnologia CMOS estática. Este fluxo de síntese física é independente de biblioteca de células, sendo capaz de realizar, sob demanda, a geração do leiaute a partir de um netlist de transistores. O método de otimização proposto faz com que este fluxo de síntese física seja capaz de realizar a geração do leiaute orientado pelas restrições de atraso, garantindo a operação do circuito na freqüência especificada pelo projetista. Este trabalho inclui também uma pesquisa sobre os principais métodos de verificação e otimização de atraso, principalmente aqueles que podem ser aplicados quando a etapa de síntese física chega ao nível de transistores. Um método de análise de timing funcional é utilizado para identificar o atraso e o caminho críticos e, com isso, guiar o método de otimização proposto. Desta forma, não existe desperdício de esforço e desempenho para reduzir o atraso de caminhos que não contribuem efetivamente para determinar a freqüência do circuito. O método proposto neste trabalho explora as possibilidades oferecidas por ser independente de biblioteca de células, mas impõe restrições aos circuitos otimizados para reduzir o impacto do dimensionamento nas etapas de geração de leiaute. O desenvolvimento de um método incremental de seleção de caminhos críticos reduziu consideravelmente o tempo de processamento sem comprometer a qualidade dos resultados. Ainda, a realização de um método seletivo de dimensionamento de transistores, possibilitado pela adaptação de um modelo de atraso pino-a-pino, permitiu reduzir significativamente o acréscimo de área decorrente da otimização e aumentou a precisão das estimativas de atraso. / This work proposes a transistor sizing-based delay optimization method especially tailored for an automatic physical synthesis flow of static CMOS combinational circuits. Such physical synthesis flow is a library-free approach which is able to perform the layout generation using a transistor netlist level description of the circuit. The integration of the proposed optimization method to the automatic physical synthesis renders possible a timing-driven layout generation flow. This work also includes a research of the major delay verification and optimization methods, mainly those that can be applied during the physical synthesis step at the transistor level. A functional timing analysis method is used to identify the critical delay and the critical paths and thus drive the proposed optimization method. Hence, there is no waste of effort to optimize paths which are not responsible for the delay of the circuit. The optimization method proposed in this work explores the advantages provided by a library-free synthesis flow and imposes restrictions to the optimized circuits in order to minimize the impact of the transistor sizing in the layout generation steps. The development of a method for incremental critical path selection reduces the CPU time consumed by the delay optimization step. A pin-to-pin gate delay model was adapted to perform a selective transistor sizing, resulting in a significantly reduction of the area overhead.

Este trabalho propõe um método de otimização de atraso, através de dimensionamento de transistores, o qual faz parte de um fluxo automático de síntese física de circuitos combinacionais em tecnologia CMOS estática. Este fluxo de síntese física é independente de biblioteca de células, sendo capaz de realizar, sob demanda, a geração do leiaute a partir de um netlist de transistores. O método de otimização proposto faz com que este fluxo de síntese física seja capaz de realizar a geração do leiaute orientado pelas restrições de atraso, garantindo a operação do circuito na freqüência especificada pelo projetista. Este trabalho inclui também uma pesquisa sobre os principais métodos de verificação e otimização de atraso, principalmente aqueles que podem ser aplicados quando a etapa de síntese física chega ao nível de transistores. Um método de análise de timing funcional é utilizado para identificar o atraso e o caminho críticos e, com isso, guiar o método de otimização proposto. Desta forma, não existe desperdício de esforço e desempenho para reduzir o atraso de caminhos que não contribuem efetivamente para determinar a freqüência do circuito. O método proposto neste trabalho explora as possibilidades oferecidas por ser independente de biblioteca de células, mas impõe restrições aos circuitos otimizados para reduzir o impacto do dimensionamento nas etapas de geração de leiaute. O desenvolvimento de um método incremental de seleção de caminhos críticos reduziu consideravelmente o tempo de processamento sem comprometer a qualidade dos resultados. Ainda, a realização de um método seletivo de dimensionamento de transistores, possibilitado pela adaptação de um modelo de atraso pino-a-pino, permitiu reduzir significativamente o acréscimo de área decorrente da otimização e aumentou a precisão das estimativas de atraso. / This work proposes a transistor sizing-based delay optimization method especially tailored for an automatic physical synthesis flow of static CMOS combinational circuits. Such physical synthesis flow is a library-free approach which is able to perform the layout generation using a transistor netlist level description of the circuit. The integration of the proposed optimization method to the automatic physical synthesis renders possible a timing-driven layout generation flow. This work also includes a research of the major delay verification and optimization methods, mainly those that can be applied during the physical synthesis step at the transistor level. A functional timing analysis method is used to identify the critical delay and the critical paths and thus drive the proposed optimization method. Hence, there is no waste of effort to optimize paths which are not responsible for the delay of the circuit. The optimization method proposed in this work explores the advantages provided by a library-free synthesis flow and imposes restrictions to the optimized circuits in order to minimize the impact of the transistor sizing in the layout generation steps. The development of a method for incremental critical path selection reduces the CPU time consumed by the delay optimization step. A pin-to-pin gate delay model was adapted to perform a selective transistor sizing, resulting in a significantly reduction of the area overhead.

No description available.

Tecnologias submicrônicas (DSM) têm inserido novos desafios ao projeto de circuitos devido a redução de geometrias, redução na tensão de alimentação, aumento da freqüência e aumento da densidade de lógica. Estas características reduzem significativamente a confiabilidade dos circuitos integrados devido a suscetibilidade a efeitos como crosstalk e acoplamento de substrato. Ainda, os efeitos da radiação são mais significantes devido as partículas com baixa energia começam a ser um problema em tecnologias DSM. Todas essas características enfatizam a necessidade de novas ferramentas de automação. Um dos objetivos desta tese é desenvolver novas ferramentas aptas a lidar com estes desafios. Esta tese é dividida em duas grandes contribuições. A primeira está relacionada com o desenvolvimento de uma nova metodologia com o objetivo de gerar circuitos otimizados em respeito ao atraso e ao consumo de potência. Um novo fluxo de projeto é apresentado na qual o circuito é otimizado no nível de transistor. Esta metodologia permite otimizar cada transistor de acordo com as capacitâncias associadas. Diferente da metodologia tradicional, o leiaute é gerado sob demanda depois do processo de otimização de transistores. Resultados mostram melhora de 11% em relação ao atraso dos circuitos e 30% de redução no consumo de potência em comparação à metodologia tradicional. A segunda contribuição está relacionada com o desenvolvimento de técnicas de geração de circuitos tolerantes a radiação. Uma técnica CWSP é usada para aplicar redundância temporal em elementos seqüenciais. Esta técnica apresenta baixa utilização de área, mas as penalidades no atraso estão totalmente relacionadas com a duração do pulso que se planeja atenuar. Além disso, uma nova metodologia de dimensionamento de transistores para falhas transientes é apresentada. A metodologia de dimensionamento é baseada em um modelo analítico. O modelo considera independente blocos de transistores PMOS e NMOS. Então, somente transistores diretamente relacionados à atenuação são dimensionados. Resultados mostram área, atraso e consumo de potência reduzido em comparação com as técnicas CWSP e TMR, permitindo o desenvolvimento de circuitos com alta freqüência. / Deep submicron (DSM) technologies have increased the challenges in circuit designs due to geometry shrinking, power supply reduction, frequency increasing and high logic density. The reliability of integrated circuits is significantly reduced as a consequence of the susceptibility to crosstalk and substrate coupling. In addition, radiation effects are also more significant because particles with low energy, without importance in older technologies, start to be a problem in DSM technologies. All these characteristics emphasize the need for new Electronic Design Automation (EDA) tools. One of the goals of this thesis is to develop EDA tools able to cope with these DSM challenges. This thesis is divided in two major contributions. The first contribution is related to the development of a new methodology able to generate optimized circuits in respect to timing and power consumption. A new design flow is proposed in which the circuit is optimized at transistor level. This methodology allows the optimization of every single transistor according to the capacitances associated to it. Different from the traditional standard cell approach, the layout is generated on demand after a transistor level optimization process. Results show an average 11% delay improvement and more than 30% power saving in comparison with the traditional design flow. The second contribution of this thesis is related with the development of techniques for radiation-hardened circuits. The Code Word State Preserving (CWSP) technique is used to apply timing redundancy into latches and flipflops. This technique presents low area overhead, but timing penalties are totally related with the glitch duration is being attenuated. Further, a new transistor sizing methodology for Single Event Transient (SET) attenuation is proposed. The sizing method is based on an analytic model. The model considers independently pull-up and pull-down blocks. Thus, only transistors directly related to the SET attenuation are sized. Results show smaller area, timing and power consumption overhead in comparison with TMR and CWSP techniques allowing the development of high frequency circuits, with lower area and power overhead.