<p> With the increased use of the internet, artificial intelligence, IoT, and wearable devices, it has become significantly critical to ensure security and confidentiality of information, particularly within these resource-constrained edge devices. The increased attentions to security and confidentially of information led to the development of computationally-secure cryptographic algorithms. At the same time, low-power sensing devices have emerged as highly promising tools for a wide range of technological applications such as diagnostics, physiological monitoring, and healthcare systems. The desire for seamless and continuous monitoring in sensing applications necessitates these devices to be compact in size and exhibit low power consumption, making them suitable for wearable or portable use with batterypowered operation.</p> <p> Keeping this objective in focus, I will structure this dissertation into the subsequent chapters. The first part (Chapter 2) will cover a theoretical analysis of the proposed Co-planar capacitivE Asymmetry SEnsing (CEASE) technique utilizing four on-die top-layer metal plates. Also, it will present the comparison with other sensing methods which are capacitive parallel and inductive sensing technique in terms of detection range through electromagnetic simulation. The second part (Chapters 3) of this this dissertation will involve explore of the concept of capacitive sensing in an IC layout and co-optimizing both the ground plane capacitance and the sensing capacitance to maximize sensitivity. It will present design of the post-processing circuits and systems with ultra-low power for sensing attacks and to prove the efficacy through the post-layout simulation results. Additionally, integration with digital SCA protection and AES-256 crypto core and checking the efficacy of the proposed method using the integrated detection and countermeasure system in post-layout simulations. Next in Chapter 4, we will show the lowest-power and the energy/conversion step time-based RDC for low frequency applications. It will presents the ways to enhance the energy-resolution trade-offs in time-based RDC, improving the rms jitter/phase noise with help of speed-up latches, to achieve higher bit-resolution. Furthermore, the power/performance trade-off in experiment through 3 different design variations optimized towards lowest energy baseline, higher resolution, and process portability tapeout and IC measurements is presented. Finally, in Chapter 5, we will show a novel proposed switchable dual-mode device that combines a high-frequency antenna and a Human Body Communication (HBC) coupler in a single device. The integration of these two modes addresses the limitations of HBC, such as restricted data transmission, and overcomes the drawbacks of signal absorption in the 24GHz frequency band by the human body. </p>

<p>        The last decade has witnessed an explosive growth in highly data-centric applications such as Internet of Things (IoT) and Artificial Intelligence (AI). Such applications demand highly efficient data storage and processing, especially when the systems operate under high energy/resource constraints, such as in intermittent-powered systems or edge AI platforms. Therefore, at the hardware level, high storage capacity along with low power operations has become more crucial than ever. Although conventional silicon-based complementary metal-oxide semiconductor (CMOS) has brought great prosperity to the semiconductor industry to date, enabling high-performance computing, increasing leakage energy and low cell density hinder their ability to sustain their benefits at scaled nodes and meet the demands of emerging data-intensive workloads. On the other hand, emerging non-volatile memories (NVMs) have gained much attention due to their distinct advantages over CMOS, such as zero leakage, high density, and non-volatility. However, they suffer from issues associated with high write power, endurance and/or variability. Thus, there is a need for new memory technologies that offer high density, low power and high-performance attributes to meet the data storage and efficiency demands of the new workloads. Furthermore, such technological advances need to be supported by architectural innovations. Despite hardware advances, the energy efficiency gains in traditional von-Neumann architectures are limited by power-hungry data movements between memory and processor, also known as the memory bottleneck. To alleviate this issue, in-memory computing (IMC) has emerged as a promising technique, wherein certain computations are executed within a memory macro, thus reducing processor-memory transactions. Along similar lines, incorporating non-volatile storage in logic state elements, such as flip-flops, has gained much attention for intermittently-powered systems, wherein the state of the processor is efficiently backed-up in the local non-volatile memory in the event of a power failure. Such techniques enabling logic-memory synergy reduce compute, storage, and/or communication costs and thus can be highly promising for future computing platforms. However, existing techniques for logic-memory fusion suffer from key design bottlenecks that need to be mitigated via extensive technology-circuit-architecture co-design. In this dissertation, we address some of the issues associated with data storage and processing by exploring spin-based low-power non-volatile devices, their memory applications, and logic-memory coupling enabled by their unique technological attributes. </p> <p>      We propose spin-based devices that employ the valley-spin Hall (VSH) effect in monolayer transition metal dichalcogenides (TMDs), such as tungsten di-selenide (WSe2). With the unique features of WSe2, the proposed devices are designed to have an integrated back-gate, enabling control of the charge and spin currents in 2D TMD channel. This design leads to an access-transistor-less compact layout in memory arrays. The generated spin currents diverge into opposite directions with out-of-plane spins, allowing for the coupling of WSe2 with perpendicular magnetic anisotropy (PMA) magnets. This enables low-power write operations and facilitates differential logic encoding within a single device. Additionally, we utilize inter-layer exchange-coupling mediated by FeCo-oxide and Ta layers to electrically isolate but magnetically couple the PMA free layers. This configuration benefits read performance by achieving low series resistance in the read path. To ensure reliable inter-layer coupling and the functionality of the proposed devices, we perform micromagnetic OOMMF simulations and extensively investigate the impact of process variations on the exchange-coupled PMA free layers. From the simulations, we conclude that the proposed design is resilient to potential process variations arising from misalignment of the PMA free layers and reductions in exchange-coupling strength. Based on the proposed devices, we explore circuit designs for logic and memory applications. </p> <p>      First, we propose VSH effect-based non-volatile flip-flops (VSH-NVFFs) using the proposed devices to introduce non-volatility in logic targeted for intermittently powered systems. The key challenge to design such systems is to enable energy-efficient data back-up in the event of power failure. In our design, we achieve high energy-efficiency via device-circuit co-design of VSH devices and NVFFs. We propose two flavors of NVFFs: NVFF-1 with a compact design and NVFF-2 targeted for lowering data restore energy. Compared to existing giant spin Hall (GSH) effect-based NVFFs, also known as spin-orbit torque or SOT-NVFFs, our NVFFs exhibit 68%-71%, 74%-75% and 55%-59% lower normal, back-up, and restore energies, respectively. Among the proposed VSH-NVFFs, NVFF-1 exhibits 8% lower operation energy than NVFF-2, while NVFF-2 exhibits 6% lower back-up energy and 11% lower restore energy. This result suggests that NVFF-1 is more suitable for systems with a smaller number of checkpointing operations (data back-up/restore), while NVFF-2 is beneficial for systems needing a larger number of checkpointing operations. Furthermore, by conducting Monte Carlo simulations, we confirm the reliable restore operation of the proposed NVFFs.</p> <p>      Secondly, we design memory arrays using the proposed devices to gain benefits over previously proposed VSH effect-based memory designs, in which read currents flow through a highly resistive 2D TMD channel, degrading read performance. For read operations, our memory array requires a read access transistor. By sharing the read access transistor per word, we minimize the area overhead in our memory array design. The area of our bit-cell is comparable to a previously proposed VSH memory, despite the inclusion of an additional read access transistor. Additionally, with the electrical isolation of the read and write paths in our design, we achieve improvements in read performance, with reductions of 39%-42% and 36%-46% in read time and energy, respectively. However, this improvement comes at the cost of write performance, with a 1.7X and 2.0X increase in write time and energy, respectively. We also achieve a 1.1X-1.3X larger sense margin (SM) and a 1.2X-1.3X improvement in read disturb margin (RDM). Furthermore, by increasing the size of the read access transistor in our memory array, we can further improve the SM by up to 1.5X-1.6X with only a 7%-12% area increase. Our design can be particularly useful for applications that involve frequent reads and few writes, such as neural accelerators.</p> <p>      We further expand our exploration of VSH effect-based devices for implementing IMC. As XNOR-based binary neural networks (BNNs) have shown immense promise for resource-intensive AI edge systems, their implementation has been explored using SRAMs and emerging NVMs. However, these designs typically need two bit-cells (2T-2R) to encode signed weights, resulting in an area overhead. Therefore, we address this issue by proposing a compact and low-power IMC technique for XNOR-based dot products. Our approach utilizes the VSH effect in monolayer WSe2 to design XNOR bit-cells that feature an access-transistor-less compact layout and differential weight encoding in a single device (XNOR-VSH). We co-optimize the proposed VSH device and the memory arrays to enable efficient in-memory dot product computations between signed binary inputs and signed binary weights. The compactness of the proposed XNOR-VSH array leads to 4.8%-9.0% lower compute latency and 36.6%-62.5% lower compute energy, along with 49.3%-64.4% smaller area compared to spin-transfer torque magnetic RAM (STT-MRAM) and SOT-MRAM based XNOR-arrays.</p> <p>      Lastly, we explore the modeling and design of voltage-controlled spintronic devices, which have shown remarkable potential for ultra-low-power and high-speed operation empowered by magnetoelectric (ME) materials. The proposed ME device utilizes a monolayer WSe2 channel placed on top of a Cr2O3 ME dielectric, which are electrostatically controlled by top and bottom gates. To capture the electrostatics in 2D TMD and the gate-voltage-dependent ME effect, we establish a modeling framework using a distributed capacitive network. This framework self-consistently accounts for the interactions between the various components. We verify the functionality of the proposed model by simulating the proposed device, and show how it can capture the device characteristics.</p>

<p>Energy efficient machine learning accelerator design</p>

<p dir="ltr">The intricate domain of chip design encompasses the creation of intricate blueprints for integrated circuits (ICs). Algorithms, pivotal in this realm, assume the role of optimizing IC performance and functionality. This thesis delves into the utilization of algorithms within chip design, spotlighting their potential to amplify design process efficiency and efficacy. Notably, this study undertakes a comprehensive comparison of algorithmic performances on both Central Processing Units (CPUs) and Graphics Processing Units (GPUs). A cornerstone application of algorithms in chip design lies in logic synthesis, which transmutes a high-level circuit description into a silicon-compatible, low-level representation. By minimizing gate requisites, curtailing power consumption, and bolstering performance, algorithms serve as architects of optimized logic synthesis. Furthermore, the arena of physical design harnesses algorithms to translate logical designs into physically realizable layouts on silicon wafers. This involves meticulous considerations like routing congestion and power efficiency. Furthermore, this thesis adopts a thorough approach by extensively exploring the implementation intricacies of two pivotal physical design algorithms. The Kernighan-Lin Partitioning Algorithm is prominently featured for optimizing Placement and Partitioning, while Lee’s Algorithm provides valuable insights for enhancing Routing. Through a meticulous comparison of dataset efficiency and run-time across both hardware platforms, noteworthy insights have emerged. In KL Algorithm, datasets categorized as small (with sizes < 105), the CPU demonstrates a 1.2X faster processing speed compared to the GPU. However, as dataset sizes surpass this threshold, a distinct trend emerges: while GPU run times remain relatively consistent, CPU run times undergo a threefold increase at select points. In the case of Lee’s Algorithm, the CPU demonstrated superior execution time despite having fewer cores and threads than the GPU. This can be attributed to the inherently sequential nature of Lee’s Algorithm, where each element depends on the preceding one, aligning with the CPU's strength in handling sequential tasks. This thesis embarks on a comprehensive analytical journey, delving into the nuanced interplay between these contrasting aspects.</p>

<p dir="ltr"> Conventional RF switching technologies struggle to simultaneously achieve high-power handling, low loss, high isolation, broadband operation, quick reconfiguration, high linearity, and low cost, which are desirable for many applications, including communications, radar, and sensors. Moreover, they require electrical bias networks, which degrade performance and, in many cases, inhibit wideband applications, including DC operation. On the other hand, plasma (photoconductive) switches use an optical bias to generate free charge carriers. Recently these switches have begun to not only rival conventional technologies in terms of performance metrics such as switching speeds and loss but have exceeded what is possible in terms of power handling. This work details the strides made in placing solid-state plasma technologies at the forefront of advanced, high-power switching applications including a novel high-power tuner and an absorptive/reflective SPnT switch. In various form factors, SSP has achieved analog control of loss as low as 0.09 dB and isolation as high as 54 dB, linearity of 68.8 dBm (IP3), 110 GHz instantaneous bandwidth, including DC, switching speeds as low as 3.5 us, 100+ W power handling, and 30+ W hot switching. In addition, comprehensive physics modeling has been developed to enable seamless design validation before fabrication commences. This thesis discusses the achievements and design considerations for creating optimized plasma switches and proposes a path for future applications.</p>

<p>In recent years, switch-mode power electronic converters have gained considerable popularity</p> <p>because of their compact size and high switching frequencies. This makes them</p> <p>suitable for power processing in various applications, including photovoltaic systems and</p> <p>electric vehicles. However, their high switching frequency capabilities have a drawback. A</p> <p>high-frequency common-mode voltage coupled with the switching of the power converters</p> <p>excites the parasitic capacitances of the system. It leads to the flow of common-mode current.</p> <p>Since the common-mode current flows through an unintended path, it can potentially</p> <p>interfere with the performance of system components. Passive filters can be used to mitigate</p> <p>common-mode currents. Using a common-mode inductor in conjunction with strategically</p> <p>placed capacitors makes it possible to limit the flow of common-mode current.</p> <p><br></p> <p>As part of this work, passive mitigation of common-mode current will be investigated in</p> <p>a variable frequency drive system. In this regard, the process of designing a three-phase ac</p> <p>common-mode inductor is explained. As a first step, a mitigation strategy is proposed and</p> <p>described. Next, the issue of self-capacitance of the inductor is discussed. Afterwards, the</p> <p>ac common-mode inductor is designed using a multi-objective optimization-based approach.</p> <p>Following this are the design results, concluding the dissertation.</p>

<p>Gastroparesis and functional dyspepsia are debilitating stomach disorders that together affect 10% of the world population. Modulating gastric function is an important target function for alternative therapies like gastric electrical stimulation (GES). The Enterra device is the only FDA approved implantable device currently available that can administer GES to entrain gastric slow wave activity. However, recent evidence has called into question the clinical utility of this system. In this work, I present the development and in vivo application of a new, closed loop, chronically implantable electroceutical device capable of continuously recording gastric motility and administering synchronous GES, that will form the needed foundation for neuromodulation protocols that can correct shortcomings in past, first-generation bioelectronic attempts to ameliorate and monitor gastric disorders. This system captures gastric serosal myoelectric activity using electrogastrography, as well as gastric contraction activity using strain gauge force transducers. I present data captured from anesthetized and freely behaving rats, demonstrating the ability of the device to capture physiologically relevant gastric motility patterns and changes, safely and effectively. I present a framework built on continuous wavelet transforms to analyze frequency and amplitude changes in captured data to inform potential therapies. I present data demonstrating the ability of the device to selectively stimulate enteric neurons in sync with gastric slow waves, resulting in a relaxation of the pyloric sphincter muscle, in a closed loop fashion. I present the development of a large animal preclinical proof-of-principle version of this system, and data captured from its implantation in freely behaving pigs, as a translational step to future human trials. In the future, this system will enable further studies into future closed loop therapies aimed at increasing gastric accommodation, stimulating physiological gastric emptying and/or pyloric opening with physiologically appropriate timing and extent. </p>

<p dir="ltr">Due to the rapidly evolving landscape of the Internet of Things (IoT), efficient<br>communication solutions are increasingly sought after. The thesis delves into<br>the development and validation of two optical communication systems (IDC,<br>2021). Capitalizing on the benefits of Optical Wireless Communication (OWC)<br>and Optical Frequency Identification(OFID), two innovative optical systems are<br>introduced: a single-pixel OFID optical reader and a computer vision-based<br>communication system that utilizes an OLED tag, a camera, and a laptop as a<br>reader. These systems are designed to surpass the challenges associated with<br>existing technologies like RFID and Bluetooth, offering enhancements in<br>security, privacy, and autonomy through the integration of energy harvesting<br>technologies. Moreover, the practical application of these systems in real-world<br>settings, such as animal and object identification, highlight their versatility<br>and potential for diverse IoT applications. The prototypes presented were<br>systematically developed and subjected to a series of evaluations to assess their<br>performance. These tests focused on measuring the communication distance<br>achieved, the power consumption of the devices, and the accuracy of data<br>transmission. The experiments demonstrated the technical feasibility of the<br>systems in real IoT environments, affirming their effectiveness in overcoming<br>distance limitations and energy efficiency challenges and providing an<br>alternative solution for accurate data transmission in environments where radio<br>communications cannot operate. These findings underscore the significance and<br>applicability of optical communications.<br>highlight<br></p>

<p dir="ltr">Sensing and communication circuits and systems are crucial components in various electronic devices and technologies. These systems are designed to acquire information from the surrounding environment through sensors, process that information, and facilitate communication between different devices or systems. It plays a vital role in modern electronic devices, enabling them to collect, process, and exchange information to perform various functions in applications such as IoB (Internet of Body), healthcare, hardware security, industrial automation, and more.</p><p dir="ltr">This work focuses on innovations in sensing and communication circuits spanning two independent application areas – human body communication and hardware emanations security.</p><p dir="ltr">First, an ultra-low power ECG monitoring system is implemented to perpetually power itself using Thermoelectric Generator (TEG) to harvest body energy while securely transmitting sensed data through on-body communication, achieving closed-loop operation without external charging or batteries. Custom circuits allow demonstrated feasibility of self-sustaining wearables leveraging Human Body Communication’s advantages.</p><p dir="ltr">Second, investigations reveal vulnerabilities introduced when repairing broken cables, with unintended monopole antennas boosting electromagnetic emissions containing signal correlations. Experiments characterize long-range detection regimes post-repair across USB keyboard cables. Further circuit and structural innovations provide localized shielding at repair points as a potential mitigation. Advancements offer contributions in understanding hardware emission security risks to inform protection strategies.</p><p dir="ltr">The two separate research work demonstrate specialized circuits advancing the state-of-the-art in sensing and communication for wearable body-based systems and hardware security through greater awareness of vulnerabilities from unintended emissions.</p><p><br></p>

<p>  </p> <p>Many machine learning models exist for battery management systems to utilize. Few have been shown to work. This work focuses on gathering data from cycling battery packs and sending this data directly to machine learning models built off robust datasets for applying the resulting predicted values and outputs directly on top of real-time systems. A parasitic sensor network was created composed of a main microcontroller, a host CPU, and various sensors including resistance temperature detection devices (RTDs), a voltage measurement circuit, current measurement circuit, and an accelerometer/gyroscope. The resulting network was integrated parasitically with a 4-cell 18650 SONY VTC6 battery pack, then tested both on-ground and in-flight with a commercial quadcopter. Real-time data for the battery pack with four cells in series was gathered. This real-time data stream was then integrated with data-driven neural network algorithms trained on various 18650 datasets and a real physical model to finalize the “AI BMS”. Using the power of non-linear models to infer battery health impacts not normally considered in battery management systems, the “AI BMS” was able to use low-fidelity real-time data in conjunction with a powerful multi-faceted model to make predictive decisions about battery health characteristics on top of normal system operations.</p>