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In this thesis, a standard flow path is proposed to establish the model library for inductors and capacitors in multilayer substrate structure. By the way of excellent agreement between simulation and measurement within self resonant frequency ¡]SRF¡^, we aimed at the demanded performance of passives in modules and adopted Pi-section equivalent circuits as basic model. Meanwhile, an automatic program on CAD-based platform is used for extraction of Pi-model circuit elements and calculation of SRF, quality ¡]Q¡^factor and modeling errors. In the end, we contributed the methodology to have the best performance of embedded passives design in multilayer substrate structure and established a completed model library for inductors and capacitors embedded in low temperature co-fired ceramic¡]LTCC¡^substrate for the design need in implementation of RF modules.

No description available.

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Power devices play key roles in the power electronics applications. In order for the power electronics designers to fully utilize the performance advantages of power devices, compact power device models are needed in the circuit simulator (Saber, P-spice, etc.). Therefore, it is very important to get accurate device models. However, there are many challenges due to the development of new power devices with new internal structure and new semiconductor materials (SiC, GaN, etc.). In this dissertation, enhanced power diode model is presented with an improvement in the reverse blocking region. In the current power diode model in the Saber circuit simulator, an empirical approach was used to describe the low-bias reverse blocking region by introducing an effect called "conduction loss," a parameter that causes a linear relationship between the device voltage and current at low bias voltages with no physics meaning. Furthermore, this term is not sufficient to accurately describe the changes to the device characteristics as the junction temperature is varied. In the enhanced model, an analytical temperature dependent model for the reverse blocking characteristics has been developed for Schottky/JBS diodes by including the thermionic-emission mechanism in the low-bias range. The newly derived model equations have been implemented in Saber circuit simulator using MAST language. An automated parameter extraction software package developed for constructing silicon (Si) and silicon carbide (SiC) power diode models, which is called DIode Model Parameter extrACtion Tools (DIMPACT). This software tool extracts the data necessary to establish a library of power diode component models and provides a method for quantitatively comparing between different types of devices and establishing performance metrics for device development. This dissertation also presents a new Saber-compatible approach for modeling the inter-electrode capacitances of the Si CoolMOSTM transistor. This new approach accurately describes all three inter-electrode capacitances (i.e., gate-drain, gate-source, and drain-source capacitances) for the full operating range of the device. The model is derived using the actual charge distribution within the device rather than assuming a lumped charge or one-dimensional charge distribution. The comparison between the simulated data with the measured results validates the accuracy of the new physical model. / Ph. D.

The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used as switching elements in LCD displays and large area matrix addressed senor arrays. In recent years, a-Si:H TFTs have been used as analog active components in OLED displays. However, a-Si:H TFTs exhibit a bias induced metastability. This problem causes both threshold voltage and subthreshold slope to shift with time when a gate bias is applied. These instabilities jeopardize the long-term performance of a-Si:H TFT circuits. Nevertheless a-Si:H TFTs show an exponential transfer characteristic in the subthreshold region. Moreover, the typical power consumptions for TFTs in the subthreshold region are in the order of nano-watts, thus making them suitable for low power design. For these reasons, a-Si:H TFT I-V characteristics in the forward subthreshold operation are investigated. First, we have derived the static and dynamic models of a-Si:H TFT in the forward subthreshold region. Second, we have verified our theoretical models with experimental results. Third, we have proven that a-Si:H TFT experiences no subthreshold slope degradation or threshold voltage shift in the forward subthreshold operation. Finally, we have studied a-Si:H TFT current mirror circuit applications. Measurements regarding the fidelity of current matching in the forward subthreshold region have been performed, and results are shown.

The hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used as switching elements in LCD displays and large area matrix addressed senor arrays. In recent years, a-Si:H TFTs have been used as analog active components in OLED displays. However, a-Si:H TFTs exhibit a bias induced metastability. This problem causes both threshold voltage and subthreshold slope to shift with time when a gate bias is applied. These instabilities jeopardize the long-term performance of a-Si:H TFT circuits. Nevertheless a-Si:H TFTs show an exponential transfer characteristic in the subthreshold region. Moreover, the typical power consumptions for TFTs in the subthreshold region are in the order of nano-watts, thus making them suitable for low power design. For these reasons, a-Si:H TFT I-V characteristics in the forward subthreshold operation are investigated. First, we have derived the static and dynamic models of a-Si:H TFT in the forward subthreshold region. Second, we have verified our theoretical models with experimental results. Third, we have proven that a-Si:H TFT experiences no subthreshold slope degradation or threshold voltage shift in the forward subthreshold operation. Finally, we have studied a-Si:H TFT current mirror circuit applications. Measurements regarding the fidelity of current matching in the forward subthreshold region have been performed, and results are shown.

In modern integrated circuits, electrostatic discharge (ESD) is a major problem that influences the reliability of operation, yield and cost of fabrication. ESD discharge events can generate static voltages beyond a few kilo volts. If these voltages are dissipated in the chip, high electric field and high current are generated and will destroy the gate oxide material or melt the metal interconnects. In order to protect the chip from these unexpected ESD events, special protection devices are designed and connect to each pin of the IC for this purpose. With the scaling of nano-metric processing technologies, the ESD design window has become more critical. That leaves little room for designers to maneuver. A good ESD protection device must have superior current sinking ability and also does not affect the normal operation of the IC. The two main categories of ESD devices are snapback and non-snapback ones. Non-snapback designs usually consist of forward biased diode strings with properties, such as low heat and power, high current carrying ability. Snapback devices use MOSFET and silicon controlled rectifier (SCR). They exploit avalanche breakdown to conduct current. In order to investigate the properties of various devices, they need to be modeled in device simulators. That process begins with realizing a technology specific NMOS and PMOS in the device simulators. The MOSFET process parameters are exported to build ESD structures. Then, by inserting ESD devices into different simulation test-benches, such as human-body model or charged-device model, their performance is evaluated through a series of figures of merit, which include peak current, voltage overshoot, capacitance, latch-up immunity and current dissipation time. A successful design can sink a large amount of current within an extremely short duration, while it should demonstrate a low voltage overshoot and capacitance. In this research work, an inter-weaving diode and SCR hybrid device demonstrated its effectiveness against tight ESD test standards is shown.

The objective of this research has been the study of device properties for emerging wide-bandgap cubic-phase semiconductors. Though the wide-bandgap semiconductors have great potential as high-power microwave devices, many gaps remain in the knowledge about their properties. The simulations in this work are designed to give insight into the performance of microwave high-power devices constructed from the materials in question. The simulation are performed using a Monte Carlo simulator which was designed from the ground up to include accurate, numerical band structures derived from an empirical pseudo-potential model. Improvements that have been made to the simulator include the generalized device structure simulation, the fully numerical final state selector, and the inclusion of the overlap integrals in the final-state selection. The first comparison that is made among the materials is direct-current breakdown. The DC voltage at which breakdown occurs is a good indication of how much power a transistor can provide. It is found that GaAs has the smallest DC breakdown, with 3C-SiC and ZB-GaN being over 3 times higher. This follows what is expected and is discussed in detail in the work. The second comparison made is the radio-frequency breakdown of the transistors. When devices are used in high-frequency applications it is possible to operate them beyond DC breakdown levels. This phenomenon is caused by the reaction time of the carriers in the device. It is important to understand this effect if these materials are used in a high-frequency application, since this effect can cause a change in the ability of a material to produce high-power devices. MESFETs made from these materials are compared and the results are discussed in detail.

This dissertation describes the study of organic thin-film solar cells in pursuit of affordable, renewable, and environmentally-friendly energy sources. Particular emphasis is given to the molecular ordering found in liquid crystalline or polycrystalline films as a way to leverage the efficiencies of these types of cells. Maximum efficiencies estimated based on excitonic character of organic solar cells show power conversion efficiencies larger than 10% are possible in principle. However, their performance is often limited due to small exciton diffusion lengths and poor transport properties which may be attributed to the amorphous nature of most organic semiconductors.Discotic liquid crystal (DLC) copper phthalocyanine was investigated as an easily processible building block for solar cells in which ordered molecular arrangements are enabled by a self-organization in its mesophases. An increase in photocurrent and a reduction in series resistance have been observed in a cell which underwent an annealing process. X-ray diffraction (XRD) and atomic force microscopy (AFM) measurements suggest that structural and morphological changes induced after the annealing process are related to these improvements.In an alternative approach, p-type pentacene thin films prepared by physical vapor deposition were incorporated into heterojunction solar cells with C60 as n-type layers. Power conversion efficiencies of 2.7 % under broadband illumination (350-900 nm) with a peak external quantum efficiency of 58 % have been achieved with the broad spectral coverage across the visible spectrum. Analysis using an exciton diffusion model shows this efficient carrier generation is mainly due to the large exciton diffusion length of pentacene films. Joint XRD and AFM studies reveal that the highly crystalline nature of pentacene films can account for the observed large exciton diffusion length. In addition, the electrical characteristics are studied as a function of light intensity using the equivalent circuit model used for inorganic pn-junction solar cells. Dependences of equivalent-circuit parameters on light intensity are further investigated using a modified equivalent circuit model, and their effects on the overall photovoltaic performance are discussed.