The focus of this thesis is on developing theories and techniques to extract lossy microwave filter parameters from data. In the literature, the Cauchy methods have been used to extract filters’ characteristic polynomials from measured scattering parameters. These methods are described and some examples are constructed to test their performance. The results suggest that the Cauchy method does not work well when the Q factors representing the loss of filters are not even. Based on some prototype filters and the relationship between Q factors and the loss, we conduct preliminary studies on alternative representations of the characteristic polynomials. The parameters in these new models are extracted using the Levenberg–Marquardt algorithm to accurately estimate characteristic polynomials and the loss information.

Power devices play key roles in the power electronics applications. In order for the power electronics designers to fully utilize the performance advantages of power devices, compact power device models are needed in the circuit simulator (Saber, P-spice, etc.). Therefore, it is very important to get accurate device models. However, there are many challenges due to the development of new power devices with new internal structure and new semiconductor materials (SiC, GaN, etc.). In this dissertation, enhanced power diode model is presented with an improvement in the reverse blocking region. In the current power diode model in the Saber circuit simulator, an empirical approach was used to describe the low-bias reverse blocking region by introducing an effect called "conduction loss," a parameter that causes a linear relationship between the device voltage and current at low bias voltages with no physics meaning. Furthermore, this term is not sufficient to accurately describe the changes to the device characteristics as the junction temperature is varied. In the enhanced model, an analytical temperature dependent model for the reverse blocking characteristics has been developed for Schottky/JBS diodes by including the thermionic-emission mechanism in the low-bias range. The newly derived model equations have been implemented in Saber circuit simulator using MAST language. An automated parameter extraction software package developed for constructing silicon (Si) and silicon carbide (SiC) power diode models, which is called DIode Model Parameter extrACtion Tools (DIMPACT). This software tool extracts the data necessary to establish a library of power diode component models and provides a method for quantitatively comparing between different types of devices and establishing performance metrics for device development. This dissertation also presents a new Saber-compatible approach for modeling the inter-electrode capacitances of the Si CoolMOSTM transistor. This new approach accurately describes all three inter-electrode capacitances (i.e., gate-drain, gate-source, and drain-source capacitances) for the full operating range of the device. The model is derived using the actual charge distribution within the device rather than assuming a lumped charge or one-dimensional charge distribution. The comparison between the simulated data with the measured results validates the accuracy of the new physical model. / Ph. D.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2005. / In RF power transistor characterisation, the designer is confronted with low impedance measurements (typically from 1 Ohm to 12 Ohm). These transistors are contained in metal-ceramic packages of which the lead widths vary with power capability. This thesis presents a high-quality fixture design with low impedance TRL calibration standards for characterisation of an LDMOS transistor. Pre-matching networks are used to transform to the low impedance environment. Since these pre-matching networks are independent of the termination impedance, the low impedance port can always be designed to comply with the same dimension as the device which is being measured.

Mercuric Iodide is the most promising of all semiconductor materials currently under investigation for use as radiation detectors at room temperature. While substantial studies have been conducted on single crystal HgI2, polycrystalline HgI2 remains a comparatively less studied form. The HgI2 films are deposited on TEC-15 LOF glass with a Tin Oxide (SnO2) coating which acts as the growth surface and front contact. The back contact, Palladium (Pd), is deposited by sputtering through a shadow mask. The films are circular in shape with an approximate diameter of 2.5 cm and thicknesses ranging from 50-600 micro m. The film has seven contact points defined by Pd electrodes for spectral response(SR) and I-V measurements. Measurements were done on the film with a visible light source. Numerical modeling helps us understand device properties and processes that take place in operation of the device. The focus of this work was to identify loss mechanisms in photoresponse, reveal fundamental device properties, and develop a quantitative device model for MSM HgI2 thin films using the DC Device modeling simulation tool MEDICI ™. The values for input parameters were chosen from literatutheory and reasonable estimates. Comprehensive studies were performed to investigate the sensitivity of SR and light I-V characteristics to each input parameter. Surface&Bulk recombinations have been investigated in this thesis. A Single, homogeneous region with all possible combinations of carrier mobilities, surface and bulk recombination parameters was not able to explain completely the measured SR. A Two-region model with the first region (0-0.5) μ m being surface&bulk recombination dominated, and the second (0.5-300) μ m bulk recombination dominated, was able to match the complete measured SR of current devices. The key parameters determined from the simulations are the mobilities, bulk lifetimes and surface-recombination velocities at the front contact for both carriers. These are consistent with expectations based upon known single crystal properties

Accurate modeling of current flow and network parameter extraction in 2-D and 3-D conductors has an important application in signal integrity of high-speed interconnects. In this thesis, we propose a new rigorous single-source Surface-Volume-Surface Electric Field Integral Equation (SVS-EFIE) for magnetostatic analysis of 2-D transmission lines and broadband resistance and inductance extraction in 3-D interconnects. Furthermore, the novel integral equation can be used for the solution of full-wave scattering problems on penetrable 2-D cylinders of arbitrary cross-section under transverse magnetic polarization. The new integral equation is derived from the classical Volume Electric Field Integral Equation (V-EFIE) by representing the electric field inside a conductor or a scatterer as a superposition of the cylindrical waves emanating from the conductor’s surface. This converts the V-EFIE into a surface integral equation involving only a single unknown function on the surface. The novel equation features a product of integral operators mapping the field from the conductor surface to its volume and back to its surface terming the new equation the Surface-Volume-Surface EFIE. The number of unknowns in the proposed SVS-EFIE is approximately the square root of the number of degrees of freedom in the traditional V-EFIE; therefore, it allows for substantially faster network parameter extraction and solutions to 2-D scattering problems without compromising the accuracy. The validation and benchmark of the numerical implementation of the Method of Moment discretization of the novel SVS-EFIE has been done via comparisons against numerical results obtained by using alternative integral equations, data found in literature, simulation results acquired from the CAD software, and analytic formulas.

Thesis (MEng)--Stellenbosch University, 2015. / ENGLISH ABSTRACT: Thorough layout verification of superconductor integrated circuits goes beyond design rule checking and parameter value extraction. The former is used to verify adherence to process design rules, and the latter to determine the element values of components such as inductors and resistors and Josephson junction critical currents. Still, neither gives much warning against subtle layout errors that could result in unintended parasitic elements, or a circuit that does not reflect the original circuit topology. A specialized implementation for Cadence Virtuoso allows layout-versus-schematic verification, but it is limited both to commercial software and in terms of its usefulness. Parameter extraction software such as InductEx is used to extract the component element values of a circuit from its layout if the circuit topology is provided as a netlist, which is mostly created by the designer. However, the element values are extracted for the supplied topology, even if a layout mistake such as creating a connection to the wrong node or a mistake in the netlist results in a model mismatch. After a failed verification, further diagnosis is required to determine whether the error is indeed in the layout or in the input topology - prolonging the verification process significantly. Here we present a free-standing layout-versus-schematic verification toolkit for superconductive integrated circuits, and discuss its implementation after systematically considering the algorithms at its core. We demonstrate results of the layout-versus-schematic verification and how the layout-versus-schematic toolkit is used as a whole in conjunction with InductEx to perform automated parameter extraction for cell-level layout verification. The current version of this toolkit provides the user with three stand-alone tools that are best used in conjunction with InductEx: A GDSII file flattener, a layout-to-schematic netlist extractor (with the option of viewing a pictorial reconstruction of the netlist and schematic) and a netlist comparison tool by which the user can determine whether a layout agrees with an input schematic. We conclude that the netlist comparison and viewing tool provides a valuable method for expediting the layout verification process, making it more efficient and minimizing the chances of mistakes. In its current form the layout-to schematic tool is still limited in that it cannot yet fully support circuits with mutual coupling. Although many improvements can still be made to this toolkit, the implemented version of these tools can already provide great benefit to Rapid Single Flux quantum (RSFQ) cell designers. / AFRIKAANSE OPSOMMING: Deeglike uitleg verifikasie van supergeleier geïntegreerde stroombane strek verder as bloot die nasien van ontwerpreëls en die onttrekking van parameter waardes. Eersgenoemde word gebruik om vas te stel of daar voldoen word aan die proses se ontwerpreëls, en laasgenoemde om die waardes van komponente soos induktors en resistors en die kritiese strome van Josephson aansluitings te bepaal. Nogtans bied nie een van hulle veel waarskuwing teen subtiele uitlegfoute wat onbeplande parasitiese elemente kan veroorsaak nie, of teen ‘n stroombaan wat nie die oorspronklike stroombaan topologie weerspieël nie. ‘n Gespesialiseerde implementasie van Cadence Virtuoso maak LVS (layout-versus-schematic) verifikasie moontlik, maar dit is beperk tot kommersiële sagteware en ook beperk in terme van bruikbaarheid. Parameter onttrekking sagteware soos InductEx word gebruik om waardes van die komponent-elemente van ‘n stroombaan vanuit die uitleg te onttrek wanneeer die stroombaan topologie as ‘n netlist, wat meestal deur die ontwerper geskep is, voorsien word. Die elementwaardes word egter onttrek volgens die topologie wat verskaf is, al is daar uitlegfoute, soos byvoorbeeld wanneer ‘n koppeling met ‘n verkeerde node plaasvind, of wanneer daar netlist foute is wat modelteenstrydighede veroorsaak. Na ‘n mislukte verifikasie poging word verdere diagnostiese stappe gedoen om te bepaal of die fout in die uitleg lê, of in die spesifieke topologie wat verskaf is, wat natuurlik die verifikasieproses aansienlik verleng. Hier stel ons ‘n vrystaande LVS verifikasie sagteware-pakket vir supergeleier geïntegreerde stroombane bekend, en bespreek, deur middel van die algoritmes wat die kern daarvan uitmaak, die implementering van hierdie sagteware-toestel. Ons bied die resultate van die LVS verifikasie aan en wys hoe die LVS sagteware toestel as geheel saam met InductEx gebruik kan word om automatiese parameter uittrekking vir sel-vlak uitleg verifikasie te berwerkstellig. Die huidige weergawe van die pakket bied die verbruiker drie alleenstaande programme wat verkieslik saam met InductEx gebruik moet word: ‘n GDSII “file flattener”, ‘n uitleg-tot-schematiese diagram netlist ekstraktor (met die opsie om ‘n herkonstruktueerde beeld van netlist en skematiese diagram te besigtig) en ‘n netlist vergelyking toestel waarmee die verbruiker kan vasstel of ‘n uitleg met ‘n oorspronklike skematiese diagram ooreenstem. Ons lei af dat die netlist vergelyking toestel ‘n waardevolle metode bied om die uitleg verifikasie proses te bespoedig en vergemaklik en die kanse van foute te minimaliseer. In sy huidige vorm is die uitleg-tot-skematiese diagram toestel beperk omdat dit nog nie stroombane met koppeling kan steun nie.

Electrical equivalent circuit modeling of active components is one of the most important approaches for modeling high-frequency high-power devices. Amongst the most used microwave devices, AlGaN/GaN HEMTs demonstrated their superior performance, making them highly suitable for 5G, wireless and satellite communications. Despite the remarkable performance of AlGaN/GaN HEMTs, these devices reside on substrates that invoke limitations on the operating-frequency, power-efficiency, and current dispersion phenomenon. Also, there is a limitation in present parameters extraction techniques being not able to consider both the substrate effect (Silicon, Silicon Carbide, and Diamond) and the asymmetrical GaN HEMT structure. In this thesis work, a single extrinsic parameters extraction technique using a single small-signal topology takes into account both the asymmetrical GaN HEMT structure and the different substrate types with their parasitic conduction will be developed and studied for the first time. Moreover, large-signal modeling using Quasi-Physical Zone Division technique has been applied to both GaN/D and GaN/SiC to model the isothermal-trapping free drain current, and combined with a new simple technique for comparing performance between active devices in terms of current-dispersion. The models were verified by simulating the small-signal S-parameters, large-signal IV characteristics, and single-tone load-pull. High accuracy was achieved compared to the measurement data available in the technical literature and obtained from fabricated devices.

According to non-stopable progress in wireless communications, it is desirable to integrate the RF front-end with the baseband building blocks of communication circuits into a one chip in the recent years. The CMOS technology advances, this is the reason why it becomes attractive for system-on-a-chip implementation, but CMOS device is getting shrink, so the channel electric field increasing and the hot carrier (HCI) effect becomes more significant. If the oxide is scaled down to less than 3 nm, then there is the possibility of soft or hard oxide breakdown (S/HBD) often takes place. As a result of the oxide trapping and interface generation is the long term performance drift and related reliability problems in devices and circuits. During the scaling and increasing chip power dissipation operating temperatures for device have also is increasing. Another reliability concern is the negative bias temperature instability (NBTI) caused by the interface traps under high temperature and negative gate voltage bias are arising while the operation temperature of devices is increasing. Parameter’s extraction is a very important part of the current electronic components modeling process, as it looking for the value of the unknown parameters in mathematical model, which represents physical behavior of given electronic component. The problem of parameter extraction is that fits electronic components mathematical model to a measured data set is an ill-posed problem and its solution is inherently difficult. This diploma thesis presents the parameter extraction, optimization methodology and verifies it on a case study of a MOSFET mathematical models (LEVEL1, LEVEL2 and LEVEL3) parameter extraction. The presented nonlinear method is based on the method of the least squares, which is solved with the aid of Levenberg- Marquardt’s algorithm.

The Schottky barrier, contact resistance and carrier mobility in carbon nanotube (CNT) field-effect transistors (FETs) are discussed in detail in this thesis. Novel extraction methods and definitions are proposed for these parameters. A technology comparison with other emerging transistor technologies and a performance projection study are also presented. A Schottky barrier height extraction method for CNTFETs considering one-dimensional (1D) conditions is developed. The methodology is applied to simulation and experimental data of CNTFETs feasible for manufacturing. Y-function-based methods (YFMs) have been applied to simulation and experimental data in order to extract a contact resistance for CNTFETs. Both extraction methods are more efficient and accurate than other conventional approaches. Practical mobility expressions are derived for CNTFETs covering the ballistic as well as the non-ballistic transport regime which enable a straightforward evaluation of the transport in CNTs. They have been applied to simulation and experimental data of devices with different channel lengths and Schottky barrier heights. A comparison of fabricated emerging transistors based on similar criteria for various application scenarios reveals CNTFETs as promising candidates to compete with Si-based technologies in low-power static and dynamic applications. A performance projection study is suggested for specific applications in terms of the studied design parameters.

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