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Power devices play key roles in the power electronics applications. In order for the power electronics designers to fully utilize the performance advantages of power devices, compact power device models are needed in the circuit simulator (Saber, P-spice, etc.). Therefore, it is very important to get accurate device models. However, there are many challenges due to the development of new power devices with new internal structure and new semiconductor materials (SiC, GaN, etc.). In this dissertation, enhanced power diode model is presented with an improvement in the reverse blocking region. In the current power diode model in the Saber circuit simulator, an empirical approach was used to describe the low-bias reverse blocking region by introducing an effect called "conduction loss," a parameter that causes a linear relationship between the device voltage and current at low bias voltages with no physics meaning. Furthermore, this term is not sufficient to accurately describe the changes to the device characteristics as the junction temperature is varied. In the enhanced model, an analytical temperature dependent model for the reverse blocking characteristics has been developed for Schottky/JBS diodes by including the thermionic-emission mechanism in the low-bias range. The newly derived model equations have been implemented in Saber circuit simulator using MAST language. An automated parameter extraction software package developed for constructing silicon (Si) and silicon carbide (SiC) power diode models, which is called DIode Model Parameter extrACtion Tools (DIMPACT). This software tool extracts the data necessary to establish a library of power diode component models and provides a method for quantitatively comparing between different types of devices and establishing performance metrics for device development. This dissertation also presents a new Saber-compatible approach for modeling the inter-electrode capacitances of the Si CoolMOSTM transistor. This new approach accurately describes all three inter-electrode capacitances (i.e., gate-drain, gate-source, and drain-source capacitances) for the full operating range of the device. The model is derived using the actual charge distribution within the device rather than assuming a lumped charge or one-dimensional charge distribution. The comparison between the simulated data with the measured results validates the accuracy of the new physical model. / Ph. D.

The MOS-gated thyristors (MGT) refer to the class of power devices that combine the ease of a MOS gate control with the superior current carrying capability of a thyristor structure for high-power applications. The MOS-controlled thyristor (MCT) is a typical MGT device. A comprehensive investigation of the reverse-biased safe operating area (RBSOA) characteristics of the MCT has been undertaken. The electrical failure mechanisms of the MCT are discussed, and the relationship between the dynamic avalanche limited RBSOA boundary of the MCT and the lower open-base transistor is identified. An analytical model based on the dynamic current gain concept is proposed to characterize the open-base transistor. For the first time, a RBSOA characteristic equation is developed for the MCT and a unified view of the RBSOA characteristics of the MCT is presented. The fundamental characteristics of the MCT are compared to those of the insulated gate bipolar transistor (IGBT) at two levels: unit-cell and multi-cell. The investigation of the unit-cell level focuses on the tradeoff between the on-state voltage drop, the turn-off loss, and the RBSOA characteristic. The investigation of the multi-cell level reveals the fundamental difference between the MCT and the IGBT in handling the non-uniform turn-off caused by the internal propagation gate delay of a large-area device. Lack of current saturation capability is identified as the main reason for the severe degradation of the turn-off capability of a large-area multi-cell MCT. The current saturation and controlled turn-on capabilities can be realized in the MGT devices with dual operation modes. For the first time, a dual operation mode MCT developed with superior current saturation capability is used to demonstrate how the dual operation device can be beneficial in the switching circuit application. The maximum controllable current density (Jmcc) is the most important characteristic of the dual operation mode MGT devices. A first-order analytic model is developed to characterize the Jmcc of the dual operation mode MGT structures compatible with the IGBT fabrication process. A new device structure with improved Jmcc characteristics is proposed and verified by both simulation and experimental results. The dissertation also carries out a comprehensive investigation of the development of power diodes. A new power diode, called the Trench Bipolar Junction Diode (TBJD), which has superior dynamic characteristics over the conventional P-i-N diode, is proposed. The TBJD controls the anode injection efficiency of the diode by the action of a reverse active transistor structure integrated into its anode junction. The reverse active transistor helps tailor an optimized on-state carrier profile to improve the diode switching characteristics. A novel self-aligned process is developed to fabricate the TBJD. Experimental characterization of the fabricated TBJD devices shows that the TBJD achieves superior dynamic characteristics without sacrificing the on-state voltage drop and the leakage current characteristics. / Ph. D.

Moore's Law influences more than just the speed of the latest microprocessor. The law drives many facets of the semiconductor realm. As Moore's Law continues to prevail, switching frequencies for electronics will rise. These increased switching frequencies will cause transient losses to be augmented, especially for power electronics. However, there has been a lack of work on how to improve the most simple semiconductor power device, the PiN diode. Therefore, considerable effort has been made to reduce switching losses in modern power semiconductor devices. Power diodes are used as a building block for almost all power electronics, especially boost converters for power factor correction. The re5earch presented in this thesis demonstrates that switching losses will be reduced when a power diode is replaced by two lower voltage diodes arranged in series. One such company, Q-speed, is already implementing such a technique [l]. The company is using two fast recovery diodes on one integrated circuit. Q-speed's results were comparable to more expensive methods to reduce switching losses such as the use of exotic materials like silicon-carbide. There have been many models to date for the PiN diode, but no research ha5 been published about this innovative idea. Research gathered in this thesis from extensive TCAD simulations and experiments will enlighten the power semiconductor field to this interesting approach.

Neste trabalho estudamos o processo de deposição do filme de silício policristalino dopado com oxigênio (SIPOS) depositado por LPCVD, a partir da mistura entre a silana (SiH4) e o óxido nitroso (N2O); para a sua aplicação como camada de passivação superficial em dispositivos de potência. As características físicas e elétricas do filme SIPOS foram analisadas em função dos seguintes parâmetros de deposição: pressão, razão gasosa entre (N2O/SiH4), espaçamento entre as lâminas de processo, tempo para a formação de uma camada de pré-oxidação entre SIPOS-Si e tempo de processo. Observamos que o espaçamento entre as lâminas de processo é um importante parâmetro de processo, pois este influi diretamente na uniformidade em espessura e na concentração de oxigênio presente nos filmes depositados. A caracterização elétrica dos filmes SIPOS foi realizada através de capacitores MSS. Verificamos a validade do modelo sobre o comportamento da condutividade elétrica em função da proporção gasosa (N2O/SiH4) proposto por Ni e Arnold. Uma vez determinado as melhores condições de processo, os filmes SIPOS foram depositados sobre diodos de potência pré processados fornecidos pela AEGIS Semicondutores Ltda. Estes diodos foram então caracterizados quanto a sua tensão de ruptura reversa e a sua corrente de fuga reversa. Os histogramas dos dados experimentais mostraram que diminuindo-se o tempo para a formação de uma camada de pré-oxidação entre a interface SIPOS-Si, temos uma diminuição da corrente reversa que flui pelo filme SIPOS. Os diodos de potência fornecidos pela Aegis Semicondutores Ltda foram projetados para suportarem uma tensão de ruptura reversa de 650 V. Os diodos passivados com SIPOS suportaram tensões de ruptura de até 1.200 V. / In this work, the SIPOS (Semi-Insulating Polycrystalline Silicon) LPCVD deposition process was studied to be applied as passivation layer in power devices. It was used a mixture of silane and nitrous oxide to promote the deposition process. The physical and electrical characteristics were analyzed in function of the follow process parameters: total pressure, gas ratio (N2O/SiH4), distance between samples in the LPCVD wafer holder; pre oxidation time and total process time. It was observed that the distance between samples in the LPCVD wafer holder is direct related to the thickness uniformity and in the oxygen concentration present in the SIPOS thin films. MSS capacitors were fabricated to perform the electrical characterization of the deposited SIPOS films. The validity of the model proposed by Ni and Arnold, to the behavior of the electrical conductivity in function of gas ratio (N2O/SiH4), was confirmed. The SIPOS thin film was deposited over pre processed diodes samples, supplied by AEGIS Semicondutores Ltda, in the best process conditions obtained in the previous experiments. The behavior of the leakage current and the breakdown voltage were analyzed. The histograms of the breakdown voltage data showed that decreasing the pre oxidation time of the SIPOS-Si interface, the leakage current through the SIPOS films decreases. The power diodes supplied by Aegis Semicondutores Ltda was designed to support a breakdown voltage of 650 V. The power diodes passivated with SIPOS films supported a breakdown voltage up to 1200 V.

Neste trabalho estudamos o processo de deposição do filme de silício policristalino dopado com oxigênio (SIPOS) depositado por LPCVD, a partir da mistura entre a silana (SiH4) e o óxido nitroso (N2O); para a sua aplicação como camada de passivação superficial em dispositivos de potência. As características físicas e elétricas do filme SIPOS foram analisadas em função dos seguintes parâmetros de deposição: pressão, razão gasosa entre (N2O/SiH4), espaçamento entre as lâminas de processo, tempo para a formação de uma camada de pré-oxidação entre SIPOS-Si e tempo de processo. Observamos que o espaçamento entre as lâminas de processo é um importante parâmetro de processo, pois este influi diretamente na uniformidade em espessura e na concentração de oxigênio presente nos filmes depositados. A caracterização elétrica dos filmes SIPOS foi realizada através de capacitores MSS. Verificamos a validade do modelo sobre o comportamento da condutividade elétrica em função da proporção gasosa (N2O/SiH4) proposto por Ni e Arnold. Uma vez determinado as melhores condições de processo, os filmes SIPOS foram depositados sobre diodos de potência pré processados fornecidos pela AEGIS Semicondutores Ltda. Estes diodos foram então caracterizados quanto a sua tensão de ruptura reversa e a sua corrente de fuga reversa. Os histogramas dos dados experimentais mostraram que diminuindo-se o tempo para a formação de uma camada de pré-oxidação entre a interface SIPOS-Si, temos uma diminuição da corrente reversa que flui pelo filme SIPOS. Os diodos de potência fornecidos pela Aegis Semicondutores Ltda foram projetados para suportarem uma tensão de ruptura reversa de 650 V. Os diodos passivados com SIPOS suportaram tensões de ruptura de até 1.200 V. / In this work, the SIPOS (Semi-Insulating Polycrystalline Silicon) LPCVD deposition process was studied to be applied as passivation layer in power devices. It was used a mixture of silane and nitrous oxide to promote the deposition process. The physical and electrical characteristics were analyzed in function of the follow process parameters: total pressure, gas ratio (N2O/SiH4), distance between samples in the LPCVD wafer holder; pre oxidation time and total process time. It was observed that the distance between samples in the LPCVD wafer holder is direct related to the thickness uniformity and in the oxygen concentration present in the SIPOS thin films. MSS capacitors were fabricated to perform the electrical characterization of the deposited SIPOS films. The validity of the model proposed by Ni and Arnold, to the behavior of the electrical conductivity in function of gas ratio (N2O/SiH4), was confirmed. The SIPOS thin film was deposited over pre processed diodes samples, supplied by AEGIS Semicondutores Ltda, in the best process conditions obtained in the previous experiments. The behavior of the leakage current and the breakdown voltage were analyzed. The histograms of the breakdown voltage data showed that decreasing the pre oxidation time of the SIPOS-Si interface, the leakage current through the SIPOS films decreases. The power diodes supplied by Aegis Semicondutores Ltda was designed to support a breakdown voltage of 650 V. The power diodes passivated with SIPOS films supported a breakdown voltage up to 1200 V.