A detailed critical review has been made of both solid state power devices and circuit topologies with emphasis on their application to high frequency electric process heating power supplies operating between 3and 30 MHz. A number of prototype units have been designed and constructed and their suitability for high frequency induction heating and dielectric heating applications investigated. Desirable qualities being robustness, tolerance to load mismatch, ease of design, simplicity and cost of constituent components as compared with present day valve equipment The experience gained in these investigations has resulted in the choice of the power MOSFET as the most appropriate device and Class E amplifier as being the most applicable circuit topology for the generation of RF power for high frequency electric process heating applications. A practical and theoretical study has been made of the limitations of the power MOSFET as a high frequency switching device. The effect of source feedback on the switching speed of T03 packaged devices has been investigated by the addition of a second source terminal in a specially modified T03 package. Novel drive circuits have been developed enabling high frequency switching of both power and RF MOSFETs. These have been employed in inverters operating at 3.3 MHz at power levels up to 600 W and at frequencies between 7 and 27 MHz at power levels over 100 W, with conversion efficiencies of up to 95%.

Dans une première partie, les travaux de thèse se sont focalisés sur la conception et l'optimisation de composants à superjonction et à tranchées profondes dans les gammes de 600V et 1200V. L'objectif est d'obtenir le meilleur compromis tenue en tension/ résistance à l'état passant pour ces gammes de tension. L'étude théorique a permis de comprendre le comportement de la tenue en tension de différents paramètres technologiques et géométriques. La tenue en tension est très sensible à l'équilibre des charges et à la verticalité des tranchées. La résistance passante, elle, est sensible à la profondeur de diffusion autour des tranchées et, plus généralement, au ratio de conduction entre la surface de la zone N et la surface totale. La structure a donc été optimisée afin de garantir le meilleur ratio " tenue en tension/résistance à l'état passant " en vue d'une réalisation technologique. De plus, les composants à Supe! rjonction nécessitent une protection en périphérie adaptée. En effet, les terminaisons surfaciques telles que les anneaux de garde ne permettent pas d'étaler la zone de charge d'espace à des profondeurs suffisantes. La terminaison qui est la plus adaptée à cette technologie est la Deep Trench Termination car elle permet de conserver l'équilibre des charges en périphérie et ne rajoute pas d'étapes technologiques supplémentaires. Cette terminaison a donc fait l'objet d'une optimisation aux cours de ces travaux de thèse. La seconde partie de mes travaux concerne la réalisation de la structure optimisée précédemment. L'optimisation de la diode à Superjonction est liée à certains paramètres technologiques pouvant s'avérer critiques pour obtenir les performances électriques désirées: la verticalité des tranchées, l'implantation des zones de type P sur les flancs des tranchées et la maîtrise de leur remplissage par un diélectrique. Afin d'assurer un parfait équilibre des charges entre les régions N et P, la fabrication des tranchées profondes a été optimisée afin d'obtenir des flancs de gravure les plus verticaux possible avec une rugosité de surface la plus faible possible. De plus, un procédé visant à obtenir une même profondeur de gravure quelle que soit l'ouverture a été mis en place afin de permettre un remplissage total des tranchées profondes avec du BenzoCycloButene (BCB). L'étude du remplissage des tranchées a permis de mettre au point un procédé permettant le remplissage des tranchées en un seul dépôt. / New technological ways allowing the realization of deep trench Superjunction devices (diodes or MOS transistors) with a deep trench termination are investigated. The aim of this work is to propose an alternative to conventional MOSFETs in high voltage range (600 V and above): the major challenge is to find the best trade-off between the two main parameters characteristics of these structures: specific on-resistance / breakdown voltage. We developed a technology based on a single N- epitaxial layer (thus reducing the realization cost) and the use of BCB filled, wide and deep trenches associated to boron doping on the trenches sidewalls. Previous works have demonstrated the feasibility of such junction termination and have led to the fabrication of a 1200 V Deep Trench Termination Diode (DT2-Diode). We chose to validate our termination technology by fabricating a Deep trench Superjunction Diode (DT-SJDiode) for 600 V applications. By means of Sentaurus TCAD 2D-simulations, we have first determined the optimal physical and geometrical parameters leading to a best "Breakdown voltage/on-resistance" trade-off. We presented technological results focusing on the more critical points: the control of deep trenches verticality by Deep Reactive Ion Etching technique, according to the Bosch process, and the trench filling with dielectric. We have studied the influence of SF6 etch and C4F8 passivation times on resulting trench verticality: the best anisotropy for 6 µm wide central trenches and 40 µm wide termination trenches is obtained for the couple SF6 (2 s)/ C4F8 (3.5 s). A thermal oxidation after the etch step allows to reduce the size of the scallops that appear on the trenches sidewalls and characteristics of the Bosch process (alternation of etch and passivation steps): the related peak-to-valley distance is lowered from 100 nm to 50 nm. Finally we have successfully filled deep and wide trenches by optimising the BCB spin-coating parameters, the high viscosity of this material rending difficult its spreading all over the wafer. We found that a dispensing rotation speed down to 100 rpm, an implementation of two 10 min rest steps improve BCB spreading and its flowing along the trenches. The BCB excess removing by reactive ion etching is under study: first encouraging results give an etch rate of 0.75 µm.min-1 with a SF6/02 gas mixture.

In Part I, the design of an ASIC control chip for a forward active clamp converter is presented. Integration of the control and drive circuit into one IC chip results in higher power density, higher reliability for the converter module. The designed ASIC control chip uses a 2.0 um N well Analog CMOS process, and is fabricated at MOSIS. The design procedures of the ASIC chip are explained, and experimental results are presented. Part II of the thesis focuses on the numerical investigation of several integratable lateral power devices. Lateral power devices are used in power IC designs because of their compatibility with analog & digital IC process. To obtain devices with high current density, large safe operating area, fast response and low cost is highly desirable for power ICs. In Part II of this thesis, several lateral power devices are discussed and simulated, including lateral IGBT, lateral MCT and double gate lateral MCTs. It is shown that lateral IGBT and lateral MCTs are good candidates for power IC applications. / Master of Science

abstract: This PhD thesis consists of three main themes. The first part focusses on modeling of Silver (Ag)-Chalcogenide glass based resistive memory devices known as the Programmable Metallization Cell (PMC). The proposed models are examined with the Technology Computer Aided Design (TCAD) simulations. In order to find a relationship between electrochemistry and carrier-trap statistics in chalcogenide glass films, an analytical mapping for electron trapping is derived. Then, a physical-based model is proposed in order to explain the dynamic behavior of the photodoping mechanism in lateral PMCs. At the end, in order to extract the time constant of ChG materials, a method which enables us to determine the carriers’ mobility with and without the UV light exposure is proposed. In order to validate these models, the results of TCAD simulations using Silvaco ATLAS are also presented in the study, which show good agreement. In the second theme of this dissertation, a new model is presented to predict single event transients in 1T-1R memory arrays as an inverter, where the PMC is modeled as a constant resistance while the OFF transistor is model as a diode in parallel to a capacitance. The model divides the output voltage transient response of an inverter into three time segments, where an ionizing particle striking through the drain–body junction of the OFF-state NMOS is represented as a photocurrent pulse. If this current source is large enough, the output voltage can drop to a negative voltage. In this model, the OFF-state NMOS is represented as the parallel combination of an ideal diode and the intrinsic capacitance of the drain–body junction, while a resistance represents an ON-state NMOS. The proposed model is verified by 3-D TCAD mixed-mode device simulations. In order to investigate the flexibility of the model, the effects of important parameters, such as ON-state PMOS resistance, doping concentration of p-region in the diode, and the photocurrent pulse are scrutinized. The third theme of this dissertation develops various models together with TCAD simulations to model the behavior of different diamond-based devices, including PIN diodes and bipolar junction transistors (BJTs). Diamond is a very attractive material for contemporary power semiconductor devices because of its excellent material properties, such as high breakdown voltage and superior thermal conductivity compared to other materials. Collectively, this research project enhances the development of high power and high temperature electronics using diamond-based semiconductors. During the fabrication process of diamond-based devices, structural defects particularly threading dislocations (TDs), may affect the device electrical properties, and models were developed to account of such defects. Recognition of their behavior helps us understand and predict the performance of diamond-based devices. Here, the electrical conductance through TD sites is shown to be governed by the Poole-Frenkel emission (PFE) for the temperature (T) range of 323 K ˂ T ˂ 423 K. Analytical models were performed to fit with experimental data over the aforementioned temperature range. Next, the Silvaco Atlas tool, a drift-diffusion based TCAD commercial software, was used to model diamond-based BJTs. Here, some field plate methods are proposed in order to decrease the surface electric field. The models used in Atlas are modified to account for both hopping transport in the impurity bands associated with high activation energies for boron doped and phosphorus doped diamond. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

No description available.

Neste trabalho estudamos o processo de deposição do filme de silício policristalino dopado com oxigênio (SIPOS) depositado por LPCVD, a partir da mistura entre a silana (SiH4) e o óxido nitroso (N2O); para a sua aplicação como camada de passivação superficial em dispositivos de potência. As características físicas e elétricas do filme SIPOS foram analisadas em função dos seguintes parâmetros de deposição: pressão, razão gasosa entre (N2O/SiH4), espaçamento entre as lâminas de processo, tempo para a formação de uma camada de pré-oxidação entre SIPOS-Si e tempo de processo. Observamos que o espaçamento entre as lâminas de processo é um importante parâmetro de processo, pois este influi diretamente na uniformidade em espessura e na concentração de oxigênio presente nos filmes depositados. A caracterização elétrica dos filmes SIPOS foi realizada através de capacitores MSS. Verificamos a validade do modelo sobre o comportamento da condutividade elétrica em função da proporção gasosa (N2O/SiH4) proposto por Ni e Arnold. Uma vez determinado as melhores condições de processo, os filmes SIPOS foram depositados sobre diodos de potência pré processados fornecidos pela AEGIS Semicondutores Ltda. Estes diodos foram então caracterizados quanto a sua tensão de ruptura reversa e a sua corrente de fuga reversa. Os histogramas dos dados experimentais mostraram que diminuindo-se o tempo para a formação de uma camada de pré-oxidação entre a interface SIPOS-Si, temos uma diminuição da corrente reversa que flui pelo filme SIPOS. Os diodos de potência fornecidos pela Aegis Semicondutores Ltda foram projetados para suportarem uma tensão de ruptura reversa de 650 V. Os diodos passivados com SIPOS suportaram tensões de ruptura de até 1.200 V. / In this work, the SIPOS (Semi-Insulating Polycrystalline Silicon) LPCVD deposition process was studied to be applied as passivation layer in power devices. It was used a mixture of silane and nitrous oxide to promote the deposition process. The physical and electrical characteristics were analyzed in function of the follow process parameters: total pressure, gas ratio (N2O/SiH4), distance between samples in the LPCVD wafer holder; pre oxidation time and total process time. It was observed that the distance between samples in the LPCVD wafer holder is direct related to the thickness uniformity and in the oxygen concentration present in the SIPOS thin films. MSS capacitors were fabricated to perform the electrical characterization of the deposited SIPOS films. The validity of the model proposed by Ni and Arnold, to the behavior of the electrical conductivity in function of gas ratio (N2O/SiH4), was confirmed. The SIPOS thin film was deposited over pre processed diodes samples, supplied by AEGIS Semicondutores Ltda, in the best process conditions obtained in the previous experiments. The behavior of the leakage current and the breakdown voltage were analyzed. The histograms of the breakdown voltage data showed that decreasing the pre oxidation time of the SIPOS-Si interface, the leakage current through the SIPOS films decreases. The power diodes supplied by Aegis Semicondutores Ltda was designed to support a breakdown voltage of 650 V. The power diodes passivated with SIPOS films supported a breakdown voltage up to 1200 V.

Neste trabalho estudamos o processo de deposição do filme de silício policristalino dopado com oxigênio (SIPOS) depositado por LPCVD, a partir da mistura entre a silana (SiH4) e o óxido nitroso (N2O); para a sua aplicação como camada de passivação superficial em dispositivos de potência. As características físicas e elétricas do filme SIPOS foram analisadas em função dos seguintes parâmetros de deposição: pressão, razão gasosa entre (N2O/SiH4), espaçamento entre as lâminas de processo, tempo para a formação de uma camada de pré-oxidação entre SIPOS-Si e tempo de processo. Observamos que o espaçamento entre as lâminas de processo é um importante parâmetro de processo, pois este influi diretamente na uniformidade em espessura e na concentração de oxigênio presente nos filmes depositados. A caracterização elétrica dos filmes SIPOS foi realizada através de capacitores MSS. Verificamos a validade do modelo sobre o comportamento da condutividade elétrica em função da proporção gasosa (N2O/SiH4) proposto por Ni e Arnold. Uma vez determinado as melhores condições de processo, os filmes SIPOS foram depositados sobre diodos de potência pré processados fornecidos pela AEGIS Semicondutores Ltda. Estes diodos foram então caracterizados quanto a sua tensão de ruptura reversa e a sua corrente de fuga reversa. Os histogramas dos dados experimentais mostraram que diminuindo-se o tempo para a formação de uma camada de pré-oxidação entre a interface SIPOS-Si, temos uma diminuição da corrente reversa que flui pelo filme SIPOS. Os diodos de potência fornecidos pela Aegis Semicondutores Ltda foram projetados para suportarem uma tensão de ruptura reversa de 650 V. Os diodos passivados com SIPOS suportaram tensões de ruptura de até 1.200 V. / In this work, the SIPOS (Semi-Insulating Polycrystalline Silicon) LPCVD deposition process was studied to be applied as passivation layer in power devices. It was used a mixture of silane and nitrous oxide to promote the deposition process. The physical and electrical characteristics were analyzed in function of the follow process parameters: total pressure, gas ratio (N2O/SiH4), distance between samples in the LPCVD wafer holder; pre oxidation time and total process time. It was observed that the distance between samples in the LPCVD wafer holder is direct related to the thickness uniformity and in the oxygen concentration present in the SIPOS thin films. MSS capacitors were fabricated to perform the electrical characterization of the deposited SIPOS films. The validity of the model proposed by Ni and Arnold, to the behavior of the electrical conductivity in function of gas ratio (N2O/SiH4), was confirmed. The SIPOS thin film was deposited over pre processed diodes samples, supplied by AEGIS Semicondutores Ltda, in the best process conditions obtained in the previous experiments. The behavior of the leakage current and the breakdown voltage were analyzed. The histograms of the breakdown voltage data showed that decreasing the pre oxidation time of the SIPOS-Si interface, the leakage current through the SIPOS films decreases. The power diodes supplied by Aegis Semicondutores Ltda was designed to support a breakdown voltage of 650 V. The power diodes passivated with SIPOS films supported a breakdown voltage up to 1200 V.

No description available.

Dans ce projet de thèse, qui s'appuie sur l'optimisation d'un réacteur de croissance du diamant et la construction d'un prototype, nous avons démontré l'épitaxie par étapes de couches de diamant, orientées (100), lourdement dopées au bore sur des couches de dopage plus faible dans le même processus, sans arrêter le plasma. Plus original, nous avons démontré la situation inverse. Nous présentons aussi des croissances assez lentes pour l'épitaxie de films d'épaisseur nanométriques avec de grands sauts de dopage, appelé delta-dopage. L'accent a été porté sur le gain en raideur des interfaces. Nous démontrons la présence d'interfaces fortement abruptes, issues de gravures in-situ optimisées, par une analyse conjointe en spectrométrie de masse à ionisation secondaire et en microscopie électronique en transmission à balayage en champ sombre annulaire aux grands angles. Des super-réseaux de dopages abrupts montrent des pics satellites de diffraction X typiques de la super-période. / The aim of this PhD thesis was to better understand the boron delta-doping of diamond over building a new Microwave Plasma Chemical Vapour Deposition reactor prototype. We succeed to grow step by step heavy on low, and more original, low on heavy boron-doped layers of (100)-oriented diamond in the same process and without stopping the plasma. We also settled growth parameters for a growth rate slow enough to get nanometre-thick homoepitaxial films with boron doping jumps over several orders of magnitude, called delta-doping. We demonstrated the presence of super-sharp interfaces, after optimized in situ etching, by joint Secondary Ion Mass Spectrometry and Scanning Tunneling Electron Microscopy at High-Angle Annular Dark Field analysis. Finally superlattices with abrupt boron doping levels have been grown; they show satellite peaks of X-ray diffraction representative of a super-period.

Fundação de Amparo à Pesquisa do Estado do Rio de Janeiro / O romance Ensaio sobre a cegueira, do escritor português José Saramago, publicado em 1995, revela profundas críticas à estrutura da sociedade hodierna, bem como sua política. Em vistas desse fato, a presente dissertação investiga as relações políticas e filosóficas presentes no romance, estabelecendo como arcabouço teórico as pesquisas do filósofi italiano Giorgio Agamben sobre o estado de exceção na série de volumes Homo Sacer, que segue a trilha deixada por Michel Foucault sobre os dispositivos de poder e saber na sociedade contemporânea. A pesquisa ora apresentada revela uma leitura do estado de exceção enquanto uma estrutura de exclusão da vida nuaatravés de uma via biopolítica que encontra no romance do escritor português um intenso questionamento sobre o homem moderno descolado de si mesmo / The presente study of the literary work of José Saramago, a portuguese writer, reveals a profound criticism to the structure of power in modern society, as well as, its politics. The hereby presented reading of the novel Ensaio sobre a cegueira, which was published in 1995, intends to perform an interpretative approach based on the studies of the Italian philosopher Giorgio Agamben Reading of the state of emergency. His work follows the studies of the French philosopher Michel Foucault regarding the power devices used by society to create a specific sort of life which is designed according to political purposes. The main thesis over which the presente work is constructed reveals that the bare life can be excluded when na emergency state is declared, and as a resoult, life can be killed