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Massive MIMO is an emerging technology for future wireless systems that has received much attention from both academia and industry recently. The most prominent feature of Massive MIMO is that the base station is equiped with a large number of antennas. It is therefore important to create scalable architectures to enable simple deployment in different configurations. In this thesis, a distributed architecture for performing the baseband processing in a massive OFDM MU-MIMO system is proposed and analyzed. The proposed architecture is based on connecting several identical nodes in a K-ary tree. It is shown that, depending on the chosen algorithms, all or most computations can be performed in a distrbuted manner. Also, the computational load of each node does not depend on the number of nodes in the tree (except for some timing issues) which implies simple scalability of the system. It is shown that it should be enough that each node contains one or two complex multipliers and a few complex adders running at a couple of hundres MHz to support specifications similar to LTE. Additionally the nodes must communicate with each other over links with data rates in the order of some Gbps. Finally, a VHDL implementation of the system is proposed. The implementation is parameterized such that a system can be generated from a given specification.

Denna rapport behandlar ett arbete skriven av åtta studenter som läste kursen TDDD96 Kandidatprojekt i programvaruutveckling vid Linköpings universitet under vårterminen 2020. Projektets syfte var att utveckla en verktygslåda i Python och C++ för att konstruera signalbehandlade kretsar. Denna verktygslåda är tänkt att användas inom laborationer i kursen TSTE87 Applikationsspecfika integrerande kretsar vid Linköpings universitet och inom forskning för utveckling av ASIC:s. Projektet resulterade i produkten B-ASIC. B-ASIC är ett bibliotek för programmeringsspråket Python som är skrivet i Python med en underliggande modul i C++. B-ASIC används för design och optimering av ASIC:s. Produkten B-ASIC erbjuder ett grafiskt användargränssnitt där användaren kan interagera med biblioteket utan programmeringskunskaper inom Python. I rapporten beskrivs hur projektarbetet har anpassats för att vara till värde för kunden och hur utvecklingsprocessen har påverkat resultatet av produkten. Projektmedlemmarna har dessutom genomfört egna undersökningar och dessa finns att läsa i slutet av rapporten.

La forte densité d'intégration et la miniaturisation des composants électroniques les rendent de plus en plus sensibles aux effets singuliers. Cette sensibilité est observée dans des environnements déjà largement étudiés (spatial, nucléaire) mais commence à apparaître au niveau du sol pour des applications grand public jusqu'à maintenant épargnées par de tels effets. Il devient ainsi indispensable pour les concepteurs et les fabricants de composants électroniques complexes (ASIC) de prédire la sensibilité de nouveaux composants ou de nouvelles technologies dès la phase de conception sans avoir besoin de les fabriquer.Cette thèse vise à élaborer une méthodologie de prédiction pour l'évaluation et le durcissement de ces circuits intégrés complexes face aux événements singuliers dans le but d'évaluer leur fiabilité avant la fabrication et ainsi réduire le coût des tests. Les phases de l'étude consistent à i) analyser le lien entre modèle physique et défaillance au niveau macroscopique afin de proposer des chaînes de prédiction, ii) mettre en œuvre les chaînes et valider les modèles associés sur des structures simples iii) appliquer et valider les méthodes de prédiction sur un cas réel de conception. / The scaling trend of highly integrated circuits makes them more and more sensitive to single event effects (SEE). This sensitivity was observed in widely studied environments (spatial, nuclear) but also in general public applications up to now spared by such effects. It has now become necessary for circuit designers to estimate the sensitivity of their circuit and new technology during the design phase and thus avoid spending efforts on unnecessary circuit manufacturing and testing.This thesis aims to develop a prediction methodology for integrated circuits evaluation and hardening face to the single event effect in order to assess their reliability before manufacturing and therefore, reduce the testing costs. The first step of the study is the analysis of the link between physical model and macroscopic failure in order establish prediction chains. The second step is the implementation of these chains and the validation of the associated models using simple circuits. The final step is the application and the validation of the prediction methods within a real integrated circuit design flow.

This dissertation explores the cost of programmability in computing devices as measured relative to fixed-function devices implementing the same functionality using the same physical fabrication technology. The central claim elevates programmability to an explicit design parameter that (1) can be rigorously defined, (2) has measurable costs amenable to high-level modeling, (3) yields a design-space with distinct regions and properties, and (4) can be usefully manipulated using computer-aided design tools. The first portion of the the work is devoted to laying a rigorous logical foundation to support both this and future work on the subject. The second portion supports the thesis within this established logical foundation, using a specific engineering problem as a narrative vehicle. The engineering problem explored is that of mechanically adding a useful degree of programmability into preexisting fixed-function logic while minimizing the added overhead. Varying criteria for usefulness are proposed and the relative costs estimated both analytically and through case-study using standard-cell logic synthesis. In the case study, a methodology for the automatic generation of reconfigurable logic highly optimized for a specific set of computing applications is demonstrated. The approach stands in contrast to traditional reconfigurable computing techniques which focus on providing general purpose functionality at the expense of substantial overheads relative to fixed-purpose implementations. / text

This thesis study presents a high speed VLSI implementation of the Rijndael Encryption Algorithm, which is selected to be the new Advanced Encryption Standard (AES) Algorithm. Both the encryption and the decryption algorithms of Rijndael are implemented as a single ASIC. Although data size is fixed to 128 bits in the AES, our implementation supports all the data sizes of the original Rijndael Algorithm. The core is optimised for both area and speed. Using 149K gates in a 0.35-&micro / m standard CMOS process, 132 MHz worst-case clock speed is achieved yielding 2.41 Gbit/s non-pipelined throughput in both encryption and decryption. iii The design has a latency of 30 clock periods for key expansion that takes 228 ns for this implementation. A single encryption or decryption of a data block requires at most 44 clock periods. The area of the chip is 12.8 mm2 including the pads. 0.35-&micro / m Standard Cell Libraries of the AMI Semiconductor Company are used in the implementation. The literature survey revealed that this implementation is the fastest published non-pipelined implementation for both encryption and decryption algorithms.

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FIR filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to IIR filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large number of these arithmetic units for its implementation. Research towards reducing the complexity of FIR filters has been going on for decades and the techniques used can be roughly divided into two categories; reduction in the number of multipliers and simplification of the multiplier implementation.  One technique to reduce the number of multipliers is to use cascaded sub-filters with lower complexity to achieve the desired specification, known as FRM. One of the sub-filters is a upsampled model filter whose band edges are an integer multiple, termed as the period L, of the target filter's band edges. Other sub-filters may include complement and masking filters which filter different parts of the spectrum to achieve the desired response. From an implementation point-of-view, time-multiplexing is beneficial because generally the allowable maximum clock frequency supported by the current state-of-the-art semiconductor technology does not correspond to the application bound sample rate. A combination of these two techniques plays a significant role towards efficient implementation of FIR filters. Part of the work presented in this dissertation is architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic model filters. These time-multiplexed FRM filters not only reduce the number of multipliers but lowers the memory usage. Although the FRM technique requires a higher number delay elements, it results in fewer memories and more energy efficient memory schemes when time-multiplexed. Different memory arrangements and memory access schemes have also been discussed and compared in terms of their efficiency when using both single and dual-port memories. An efficient pipelining scheme has been proposed which reduces the number of pipelining registers while achieving similar clock frequencies. The single optimal point where the number of multiplications is minimum for non-time-multiplexed FRM filters is shown to become a function of both the period, L and time-multiplexing factor, M. This means that the minimum number of multipliers does not always correspond to the minimum number of multiplications which also increases the flexibility of implementation. These filters are shown to achieve power reduction between 23% and 68% for the considered examples. To simplify the multiplier, alternate number systems like the LNS have been used to implement FIR filters, which reduces the multiplications to additions. FIR filters are realized by directly designing them using ILP in the LNS domain in the minimax sense using finite word length constraints. The branch and bound algorithm, a typical algorithm to implement ILP problems, is implemented based on LNS integers and several branching strategies are proposed and evaluated. The filter coefficients thus obtained are compared with the traditional finite word length coefficients obtained in the linear domain. It is shown that LNS FIR filters provide a better approximation  error compared to a standard FIR filter for a given coefficient word length. FIR filters also offer an opportunity in complexity reduction by implementing the multipliers using Booth or standard high-radix multiplication. Both of these multiplication schemes generate pre-computed multiples of the multiplicand which are then selected based on the encoded bits of the multiplier. In TDF FIR filters, one input data is multiplied with a number of coefficients and complexity can be reduced by sharing the pre-computation of the multiplies of the input data for all multiplications. Part of this work includes a systematic and unified approach to the design of such computation sharing multipliers and a comparison of the two forms of multiplication. It also gives closed form expressions for the cost of different parts of multiplication and gives an overview of various ways to implement the select unit with respect to the design of multiplexers. Particle filters are used to solve problems that require estimation of a system. Improved resampling schemes for reducing the latency of the resampling stage is proposed which uses a pre-fetch technique to reduce the latency between 50% to 95%  dependent on the number of pre-fetches. Generalized division-free architectures and compact memory structures are also proposed that map to different resampling algorithms and also help in reducing the complexity of the multinomial resampling algorithm and reduce the number of memories required by up to 50%.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / A programmable RF ASIC is described which provides most of the RF functions within a next generation S-band transponder for space applications. The unique 18-contact LCC device can be programmed to perform a variety of RF and analog functions. This single space qualified high speed bipolar "function toolbox" is used in 39 locations throughout the transponder to provide a flexible radio architecture. The ASIC design process, internal electrical design, circuit application, space environment performance, and RF testing of the RF ASIC are described. This proprietary part provides a space-qualified solution for RF circuitry that can be applied to a variety of space application products.

International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / NASA’s use of high bandwidth packetized Consultative Committee for Space Data Systems (CCSDS) telemetry in future missions presents a great challenge to ground data system developers. These missions, including the Earth Observing System (EOS), call for high data rate interfaces and small packet sizes. Because each packet requires a similar amount of protocol processing, high data rates and small packet sizes dramatically increase the real-time workload on ground packet processing systems. NASA’s Goddard Space Flight Center has been developing packet processing subsystems for more than twelve years. Implementations of these subsystems have ranged from mini-computers to single-card VLSI multiprocessor subsystems. The latter subsystem, known as the VLSI Packet Processor, was first deployed in 1991 for use in support of the Solar Anomalous & Magnetospheric Particle Explorer (SAMPEX) mission. An upgraded version of this VMEBus card, first deployed for Space Station flight hardware verification, has demonstrated sustained throughput of up to 50 Megabits per second and 15,000 packets per second. Future space missions including EOS will require significantly higher data and packet rate performance. A new approach to packet processing is under development that will not only increase performance levels by at least a factor of six but also reduce subsystem replication costs by a factor of five. This paper will discuss the development of a next generation packet processing subsystem and the architectural changes necessary to achieve a thirty-fold improvement in the performance/price of real-time packet processing.