In modern integrated circuits, electrostatic discharge (ESD) is a major problem that influences the reliability of operation, yield and cost of fabrication. ESD discharge events can generate static voltages beyond a few kilo volts. If these voltages are dissipated in the chip, high electric field and high current are generated and will destroy the gate oxide material or melt the metal interconnects. In order to protect the chip from these unexpected ESD events, special protection devices are designed and connect to each pin of the IC for this purpose. With the scaling of nano-metric processing technologies, the ESD design window has become more critical. That leaves little room for designers to maneuver. A good ESD protection device must have superior current sinking ability and also does not affect the normal operation of the IC. The two main categories of ESD devices are snapback and non-snapback ones. Non-snapback designs usually consist of forward biased diode strings with properties, such as low heat and power, high current carrying ability. Snapback devices use MOSFET and silicon controlled rectifier (SCR). They exploit avalanche breakdown to conduct current. In order to investigate the properties of various devices, they need to be modeled in device simulators. That process begins with realizing a technology specific NMOS and PMOS in the device simulators. The MOSFET process parameters are exported to build ESD structures. Then, by inserting ESD devices into different simulation test-benches, such as human-body model or charged-device model, their performance is evaluated through a series of figures of merit, which include peak current, voltage overshoot, capacitance, latch-up immunity and current dissipation time. A successful design can sink a large amount of current within an extremely short duration, while it should demonstrate a low voltage overshoot and capacitance. In this research work, an inter-weaving diode and SCR hybrid device demonstrated its effectiveness against tight ESD test standards is shown.

abstract: Semiconductor nanowires have the potential to emerge as the building blocks of next generation field-effect transistors, logic gates, solar cells and light emitting diodes. Use of Gallium Nitride (GaN) and other wide bandgap materials combines the advantages of III-nitrides along with the enhanced mobility offered by 2-dimensional confinement present in nanowires. The focus of this thesis is on developing a low field mobility model for a GaN nanowire using Ensemble Monte Carlo (EMC) techniques. A 2D Schrödinger-Poisson solver and a one-dimensional Monte Carlo solver is developed for an Aluminum Gallium Nitride/Gallium Nitride Heterostructure nanowire. A GaN/AlN/AlGaN heterostructure device is designed which creates 2-dimensional potential well for electrons. The nanowire is treated as a quasi-1D system in this work. A self-consistent 2D Schrödinger-Poisson solver is designed which determines the subband energies and the corresponding wavefunctions of the confined system. Three scattering mechanisms: acoustic phonon scattering, polar optical phonon scattering and piezoelectric scattering are considered to account for the electron phonon interactions in the system. Overlap integrals and 1D scattering rate expressions are derived for all the mechanisms listed. A generic one-dimensional Monte Carlo solver is also developed. Steady state results from the 1D Monte Carlo solver are extracted to determine the low field mobility of the GaN nanowires. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2017

abstract: Scaling of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) towards shorter channel lengths, has lead to an increasing importance of quantum effects on the device performance. Until now, a semi-classical model based on Monte Carlo method for instance, has been sufficient to address these issues in silicon, and arrive at a reasonably good fit to experimental mobility data. But as the semiconductor world moves towards 10nm technology, many of the basic assumptions in this method, namely the very fundamental Fermi’s golden rule come into question. The derivation of the Fermi’s golden rule assumes that the scattering is infrequent (therefore the long time limit) and the collision duration time is zero. This thesis overcomes some of the limitations of the above approach by successfully developing a quantum mechanical simulator that can model the low-field inversion layer mobility in silicon MOS capacitors and other inversion layers as well. It solves for the scattering induced collisional broadening of the states by accounting for the various scattering mechanisms present in silicon through the non-equilibrium based near-equilibrium Green’s Functions approach, which shall be referred to as near-equilibrium Green’s Function (nEGF) in this work. It adopts a two-loop approach, where the outer loop solves for the self-consistency between the potential and the subband sheet charge density by solving the Poisson and the Schrödinger equations self-consistently. The inner loop solves for the nEGF (renormalization of the spectrum and the broadening of the states), self-consistently using the self-consistent Born approximation, which is then used to compute the mobility using the Green-Kubo Formalism. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

The Schottky barrier, contact resistance and carrier mobility in carbon nanotube (CNT) field-effect transistors (FETs) are discussed in detail in this thesis. Novel extraction methods and definitions are proposed for these parameters. A technology comparison with other emerging transistor technologies and a performance projection study are also presented. A Schottky barrier height extraction method for CNTFETs considering one-dimensional (1D) conditions is developed. The methodology is applied to simulation and experimental data of CNTFETs feasible for manufacturing. Y-function-based methods (YFMs) have been applied to simulation and experimental data in order to extract a contact resistance for CNTFETs. Both extraction methods are more efficient and accurate than other conventional approaches. Practical mobility expressions are derived for CNTFETs covering the ballistic as well as the non-ballistic transport regime which enable a straightforward evaluation of the transport in CNTs. They have been applied to simulation and experimental data of devices with different channel lengths and Schottky barrier heights. A comparison of fabricated emerging transistors based on similar criteria for various application scenarios reveals CNTFETs as promising candidates to compete with Si-based technologies in low-power static and dynamic applications. A performance projection study is suggested for specific applications in terms of the studied design parameters.

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abstract: Silicon photonic technology continues to dominate the solar industry driven by steady improvement in device and module efficiencies. Currently, the world record conversion efficiency (~26.6%) for single junction silicon solar cell technologies is held by silicon heterojunction (SHJ) solar cells based on hydrogenated amorphous silicon (a-Si:H) and crystalline silicon (c-Si). These solar cells utilize the concept of carrier selective contacts to improve device efficiencies. A carrier selective contact is designed to optimize the collection of majority carriers while blocking the collection of minority carriers. In the case of SHJ cells, a thin intrinsic a-Si:H layer provides crucial passivation between doped a-Si:H and the c-Si absorber that is required to create a high efficiency cell. There has been much debate regarding the role of the intrinsic a-Si:H passivation layer on the transport of photogenerated carriers, and its role in optimizing device performance. In this work, a multiscale model is presented which utilizes different simulation methodologies to study interfacial transport across the intrinsic a-Si:H/c-Si heterointerface and through the a-Si:H passivation layer. In particular, an ensemble Monte Carlo simulator was developed to study high field behavior of photogenerated carriers at the intrinsic a-Si:H/c-Si heterointerface, a kinetic Monte Carlo program was used to study transport of photogenerated carriers across the intrinsic a-Si:H passivation layer, and a drift-diffusion model was developed to model the behavior in the quasi-neutral regions of the solar cell. This work reports de-coupled and self-consistent simulations to fully understand the role and effect of transport across the a-Si:H passivation layer in silicon heterojunction solar cells, and relates this to overall solar cell device performance. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2019

<p>        The last decade has witnessed an explosive growth in highly data-centric applications such as Internet of Things (IoT) and Artificial Intelligence (AI). Such applications demand highly efficient data storage and processing, especially when the systems operate under high energy/resource constraints, such as in intermittent-powered systems or edge AI platforms. Therefore, at the hardware level, high storage capacity along with low power operations has become more crucial than ever. Although conventional silicon-based complementary metal-oxide semiconductor (CMOS) has brought great prosperity to the semiconductor industry to date, enabling high-performance computing, increasing leakage energy and low cell density hinder their ability to sustain their benefits at scaled nodes and meet the demands of emerging data-intensive workloads. On the other hand, emerging non-volatile memories (NVMs) have gained much attention due to their distinct advantages over CMOS, such as zero leakage, high density, and non-volatility. However, they suffer from issues associated with high write power, endurance and/or variability. Thus, there is a need for new memory technologies that offer high density, low power and high-performance attributes to meet the data storage and efficiency demands of the new workloads. Furthermore, such technological advances need to be supported by architectural innovations. Despite hardware advances, the energy efficiency gains in traditional von-Neumann architectures are limited by power-hungry data movements between memory and processor, also known as the memory bottleneck. To alleviate this issue, in-memory computing (IMC) has emerged as a promising technique, wherein certain computations are executed within a memory macro, thus reducing processor-memory transactions. Along similar lines, incorporating non-volatile storage in logic state elements, such as flip-flops, has gained much attention for intermittently-powered systems, wherein the state of the processor is efficiently backed-up in the local non-volatile memory in the event of a power failure. Such techniques enabling logic-memory synergy reduce compute, storage, and/or communication costs and thus can be highly promising for future computing platforms. However, existing techniques for logic-memory fusion suffer from key design bottlenecks that need to be mitigated via extensive technology-circuit-architecture co-design. In this dissertation, we address some of the issues associated with data storage and processing by exploring spin-based low-power non-volatile devices, their memory applications, and logic-memory coupling enabled by their unique technological attributes. </p> <p>      We propose spin-based devices that employ the valley-spin Hall (VSH) effect in monolayer transition metal dichalcogenides (TMDs), such as tungsten di-selenide (WSe2). With the unique features of WSe2, the proposed devices are designed to have an integrated back-gate, enabling control of the charge and spin currents in 2D TMD channel. This design leads to an access-transistor-less compact layout in memory arrays. The generated spin currents diverge into opposite directions with out-of-plane spins, allowing for the coupling of WSe2 with perpendicular magnetic anisotropy (PMA) magnets. This enables low-power write operations and facilitates differential logic encoding within a single device. Additionally, we utilize inter-layer exchange-coupling mediated by FeCo-oxide and Ta layers to electrically isolate but magnetically couple the PMA free layers. This configuration benefits read performance by achieving low series resistance in the read path. To ensure reliable inter-layer coupling and the functionality of the proposed devices, we perform micromagnetic OOMMF simulations and extensively investigate the impact of process variations on the exchange-coupled PMA free layers. From the simulations, we conclude that the proposed design is resilient to potential process variations arising from misalignment of the PMA free layers and reductions in exchange-coupling strength. Based on the proposed devices, we explore circuit designs for logic and memory applications. </p> <p>      First, we propose VSH effect-based non-volatile flip-flops (VSH-NVFFs) using the proposed devices to introduce non-volatility in logic targeted for intermittently powered systems. The key challenge to design such systems is to enable energy-efficient data back-up in the event of power failure. In our design, we achieve high energy-efficiency via device-circuit co-design of VSH devices and NVFFs. We propose two flavors of NVFFs: NVFF-1 with a compact design and NVFF-2 targeted for lowering data restore energy. Compared to existing giant spin Hall (GSH) effect-based NVFFs, also known as spin-orbit torque or SOT-NVFFs, our NVFFs exhibit 68%-71%, 74%-75% and 55%-59% lower normal, back-up, and restore energies, respectively. Among the proposed VSH-NVFFs, NVFF-1 exhibits 8% lower operation energy than NVFF-2, while NVFF-2 exhibits 6% lower back-up energy and 11% lower restore energy. This result suggests that NVFF-1 is more suitable for systems with a smaller number of checkpointing operations (data back-up/restore), while NVFF-2 is beneficial for systems needing a larger number of checkpointing operations. Furthermore, by conducting Monte Carlo simulations, we confirm the reliable restore operation of the proposed NVFFs.</p> <p>      Secondly, we design memory arrays using the proposed devices to gain benefits over previously proposed VSH effect-based memory designs, in which read currents flow through a highly resistive 2D TMD channel, degrading read performance. For read operations, our memory array requires a read access transistor. By sharing the read access transistor per word, we minimize the area overhead in our memory array design. The area of our bit-cell is comparable to a previously proposed VSH memory, despite the inclusion of an additional read access transistor. Additionally, with the electrical isolation of the read and write paths in our design, we achieve improvements in read performance, with reductions of 39%-42% and 36%-46% in read time and energy, respectively. However, this improvement comes at the cost of write performance, with a 1.7X and 2.0X increase in write time and energy, respectively. We also achieve a 1.1X-1.3X larger sense margin (SM) and a 1.2X-1.3X improvement in read disturb margin (RDM). Furthermore, by increasing the size of the read access transistor in our memory array, we can further improve the SM by up to 1.5X-1.6X with only a 7%-12% area increase. Our design can be particularly useful for applications that involve frequent reads and few writes, such as neural accelerators.</p> <p>      We further expand our exploration of VSH effect-based devices for implementing IMC. As XNOR-based binary neural networks (BNNs) have shown immense promise for resource-intensive AI edge systems, their implementation has been explored using SRAMs and emerging NVMs. However, these designs typically need two bit-cells (2T-2R) to encode signed weights, resulting in an area overhead. Therefore, we address this issue by proposing a compact and low-power IMC technique for XNOR-based dot products. Our approach utilizes the VSH effect in monolayer WSe2 to design XNOR bit-cells that feature an access-transistor-less compact layout and differential weight encoding in a single device (XNOR-VSH). We co-optimize the proposed VSH device and the memory arrays to enable efficient in-memory dot product computations between signed binary inputs and signed binary weights. The compactness of the proposed XNOR-VSH array leads to 4.8%-9.0% lower compute latency and 36.6%-62.5% lower compute energy, along with 49.3%-64.4% smaller area compared to spin-transfer torque magnetic RAM (STT-MRAM) and SOT-MRAM based XNOR-arrays.</p> <p>      Lastly, we explore the modeling and design of voltage-controlled spintronic devices, which have shown remarkable potential for ultra-low-power and high-speed operation empowered by magnetoelectric (ME) materials. The proposed ME device utilizes a monolayer WSe2 channel placed on top of a Cr2O3 ME dielectric, which are electrostatically controlled by top and bottom gates. To capture the electrostatics in 2D TMD and the gate-voltage-dependent ME effect, we establish a modeling framework using a distributed capacitive network. This framework self-consistently accounts for the interactions between the various components. We verify the functionality of the proposed model by simulating the proposed device, and show how it can capture the device characteristics.</p>

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