Indium Tin Oxide (ITO) films were deposited on a number of semi-conductor materials using reactive r. f sputtering technique to form both rectifying Schottky and ohmic contacts. These contacts were applied in the fabrication of a number of novel optoelectronic devices: Schottky photo-diodes, transparent gate High Electron Mobility Transistors (HEMTs), heterojunction bipolar transistors (HBTs) being used as heterojunction phototransistors (HPTs), light emitting diodes (LEDs) and vertical cavity surface emitting lasers (VCSELs). A number ofthese novel devices were studied in comparatively greater detail; these were the Schottky diode and the HPT. Deposition conditions necessary to produce ITO films with high conductivity and optical transparency over a wide spectral range were studied and optimised. Separate post deposition techniques were developed to produce near ideal rectifying contacts and ohmic contacts with low contact resistance respectively. A thin film of indium (In) was also used to optimise ITO ohmic contacts to n + - GaAs substrates. Near ideal Schottky diodes were realised on n-GaAs substrates using aluminium (AI) and gold (Au) metal contacts. A simulation model was then developed and implemented to study the behaviour of current transport mechanisms over a wide temperature range. Photodiodes with ITO as the Schottky metal contact were fabricated and a study comprising of both their electrical and optical behaviour was undertaken. Relatively large geometry HBTs and HPTs were fabricated using AIGaAs/GaAs, InGaP/GaAs and InPlInGaAs systems respectively; the latter devices were first reported as a result of this study. A comparative study between devices fabricated from these systems were then made. This was followed by an appraisal of the electrical properties of each of their optical counterparts which had ITO emitter contacts. The specific photo responsivity and the spectral responses of these HPTs were analysed. In light of HPTs with transparent ITO emitter ohmic contacts, a brief examination of the merits of vertical versus lateral illumination was also made in this work. Finally a spectral response model was developed to understand and help design optoelectronic detectors comprising of single layer devices (n-GaAs Schottky photo diodes) or multiple semiconductor materials (HPTs using AIGaAs/GaAs or InPlInGaAs systems) to help predict responsivities at a given incident wavelength. As well as material properties of the constituent semiconductors, this model takes into account the specific lateral and vertical geometrical dimensions of the device.

No description available.

Noise and linearity are the two key concerns in RF transceiver systems. However, the impact of circuit topology and device technology on systems noise and linearity behaviors is poorly understood because of the complexity and diversity involved. There are two general questions that are addressed by the RF device and circuit designers: for a given device technology, how best to optimize the circuit topology; and for a given circuit topology, how best to optimize the device technology to improve the noise and linearity performance. In this dissertation, a systematic noise and linearity calculation method is proposed. This approach offers simple and analytical solutions to optimize the noise and linearity characteristics of integrated circuits. Supported by this approach, the physics of state-of-the-art SiGe HBT technology devices can be decoupled and studied. The corresponding impact on noise and linearity is investigated. New optimization methodologies for noise and linearity at both the device and circuit level are presented. In addition, this thesis demonstrates a technique that accurately extracts ac and noise parameters of devices/circuits in the millimeter-wave range. The extraction technique supports and verifies the device/circuit noise analysis from a measurement standpoint.

This thesis presents a comprehensive assessment of breakdown and operational voltage constraints in state-of-the-art silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) BiCMOS technology. Technology scaling of SiGe HBTs for high frequency performance results on lower breakdown voltages, making operating voltage constraints an increasingly vital reliability consideration in SiGe HBTs from both a device and circuits perspective.

In this work a new current-sweep stress methodology for quantitatively assessing the mixed-mode reliability (simultaneous application of high current and high voltage) of advanced SiGe HBTs is presented. This stress methodology allows one to quickly obtain the complete damage spectrum of a given device from a particular technology platform, enabling better understanding of the complex voltage, current, and temperature interdependence associated with electrical stress and burn-in of advanced transistors. We consistently observed three distinct regions of mixed-mode damage in SiGe HBTs, and find that hot carrier induced damage can be introduced into SiGe HBTs under surprisingly modest mixed-mode stress conditions. For more aggressively scaled silicon-germanium technology generations, a larger percentage of hot carriers generated in the collector-base junction are able to travel to and hence damage the EB spacer, leading to enhanced forward-mode base current leakage under stress. A new self-heating induced mixed-mode annealing effect was observed for the first time under fairly high voltage and current stress conditions, and a new damage mechanism was observed under very high voltage and current conditions. Finally, as an example of the utility of our stress methodology, we quantified the composite mixed-mode damage spectrum of a commercial third-generation (200 GHz) generation SiGe HBT. It is found that if devices are stressed with either voltage or current alone during burn-in, they can easily withstand extreme over-stress conditions. Unfortunately, devices were easily damaged when stressed with a combination of stress voltage and current, and this has significant implications for the device and circuit lifetime prediction under realistic mixed-signal operating conditions.

Field-effect transistor technologies have been critical building blocks for satellite systems since their introduction into the microelectronics industry. The extremely high cost of launching payloads into orbit necessitates systems to have small form factor, ultra low-power consumption, and reliable lifetime operation, while satisfying the performance requirements of a given application. Silicon-based complementary metal-oxide-semiconductors (Si CMOS) have traditionally been able to adequately meet these demands when coupled with radiation hardening techniques that have been developed over years of invested research. However, as customer demands increase, pushing the limits of system throughput, noise, and speed, alternative technologies must be employed. Silicon-germanium BiCMOS platforms have been identfied as a technology candidate for meeting the performance criteria of these pioneering satellite systems and deep space applications, contingent on their ability to be hardened to radiation-induced damage. Given that SiGe technology is a relative new- comer to terrestrial and extra-terrestrial applications in radiation-rich environments, the same wealth of knowledge of time-tested radiation hardening methodologies has not been established as it has for Si CMOS. Although SiGe BiCMOS technology has been experimentally proven to be inherently tolerant to total-ionizing dose damage mechanism, the single event susceptibility of this technology remains a primary concern. The objective of this research is to characterize the physical mechanisms that drive the origination of ion-induced transient terminal currents in SiGe HBTs that subsequently lead to a wide range of possible single event phenomena. Building upon this learning, a variety of device-level hardening methodologies are explored and tested for efficacy.

This thesis presents the theoretical and experimental framework for the development of accurate on-wafer S-parameter and noise parameter measurements of silicon devices in the upper millimetre-wave frequency range between 70 GHz and 300 GHz. Novel integrated noise parameter test setups were developed for nanoscale MOSFETs and SiGe HBTs and validated up to 170 GHz. In the absence of accurate foundry models in this frequency range, the experimental findings of this thesis have been employed by other graduate students to design the first noise and input impedance matched W- and D-band low-noise amplifiers in nanoscale CMOS and SiGe BiCMOS technologies. The results of the D-band S-parameter characterization techniques and of the new Y-parameter based noise model have been used by STMicroelectronics to optimize the SiGe HBT structure for applications in the D-band. In the first half of the thesis, theoretical analysis indicates that, for current silicon devices, distributive effects in test structure parasitics will become significant only beyond 300 GHz. This conclusion is supported by experiments which compare the lumped-element based open-short and the transmission line based split-thru de-embedding techniques to the multiline thru-reflect-line (TRL) network analyzer calibration algorithm. Electromagnetic simulations and measurements up to 170 GHz demonstrate that, for microstrip transmission lines with metal ground plane placed above the silicon substrate, the line capacitance per unit length remains a weak function of frequency. Based on this observation, the multiline TRL algorithm has been modified to include a dummy short de-embedding structure. This allowed for the first time to perform single step calibration and de-embedding of silicon devices using on-silicon calibration standards. The usefulness of the proposed method was demonstrated on the extraction of the difficult-to-measure SiGe HBT and nanoscale MOSFET model parameters, including transcondutance delay, tau, gate resistance, source resistance, drain-source capacitance, and channel resistance, Ri. Building on the small-signal characterization technique developed in the first half, a new Y-parameter based noise model for SiGe HBTs, that includes the correlation between the base and collector shot noise currents, is proposed in the second half of the thesis along with a method to extract the noise transit time parameter. With this model, the high frequency noise parameters of a SiGe HBT can be calculated from the measured Y-parameters, without requiring any noise figure measurements. Finally, to validate the proposed noise model, the first on-wafer integrated noise parameter measurement systems were designed and measured in the W- and D-bands. The systems enable millimetre-wave noise parameter measurements with the multi-impedance method by integrating the impedance tuner and an entire millimetre-wave noise receiver on the same die as the device-under-test. Good agreement was obtained between the noise parameters calculated from the Y-parameter measurements and those obtained from direct noise figure measurements with the integrated systems. The results indicate that the minimum noise figure of state-of-the-art advanced SiGe HBTs remains below 5 dB throughout the D-band, making them suitable for a variety of commercial products in this frequency range.

This thesis presents the theoretical and experimental framework for the development of accurate on-wafer S-parameter and noise parameter measurements of silicon devices in the upper millimetre-wave frequency range between 70 GHz and 300 GHz. Novel integrated noise parameter test setups were developed for nanoscale MOSFETs and SiGe HBTs and validated up to 170 GHz. In the absence of accurate foundry models in this frequency range, the experimental findings of this thesis have been employed by other graduate students to design the first noise and input impedance matched W- and D-band low-noise amplifiers in nanoscale CMOS and SiGe BiCMOS technologies. The results of the D-band S-parameter characterization techniques and of the new Y-parameter based noise model have been used by STMicroelectronics to optimize the SiGe HBT structure for applications in the D-band. In the first half of the thesis, theoretical analysis indicates that, for current silicon devices, distributive effects in test structure parasitics will become significant only beyond 300 GHz. This conclusion is supported by experiments which compare the lumped-element based open-short and the transmission line based split-thru de-embedding techniques to the multiline thru-reflect-line (TRL) network analyzer calibration algorithm. Electromagnetic simulations and measurements up to 170 GHz demonstrate that, for microstrip transmission lines with metal ground plane placed above the silicon substrate, the line capacitance per unit length remains a weak function of frequency. Based on this observation, the multiline TRL algorithm has been modified to include a dummy short de-embedding structure. This allowed for the first time to perform single step calibration and de-embedding of silicon devices using on-silicon calibration standards. The usefulness of the proposed method was demonstrated on the extraction of the difficult-to-measure SiGe HBT and nanoscale MOSFET model parameters, including transcondutance delay, tau, gate resistance, source resistance, drain-source capacitance, and channel resistance, Ri. Building on the small-signal characterization technique developed in the first half, a new Y-parameter based noise model for SiGe HBTs, that includes the correlation between the base and collector shot noise currents, is proposed in the second half of the thesis along with a method to extract the noise transit time parameter. With this model, the high frequency noise parameters of a SiGe HBT can be calculated from the measured Y-parameters, without requiring any noise figure measurements. Finally, to validate the proposed noise model, the first on-wafer integrated noise parameter measurement systems were designed and measured in the W- and D-bands. The systems enable millimetre-wave noise parameter measurements with the multi-impedance method by integrating the impedance tuner and an entire millimetre-wave noise receiver on the same die as the device-under-test. Good agreement was obtained between the noise parameters calculated from the Y-parameter measurements and those obtained from direct noise figure measurements with the integrated systems. The results indicate that the minimum noise figure of state-of-the-art advanced SiGe HBTs remains below 5 dB throughout the D-band, making them suitable for a variety of commercial products in this frequency range.

A summary of total dose effects observe in advanced Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) is presented in this work. The principal driving froces behin the increased use of SiGe BiCMOS technology in space based electronics systems are outlined in the motivation Section of Chapter I. This is followed by a discussion of the strained layer Si/SiGe material structure and relevant fabrication techniques used in the development of the first generation of this technology. A comprehensive description of the device performance is presented. Chapter II presents an overview of radiation physics as it applies to microelectronic devices. Several sources of radiation are discussed including the environments encountered by satellites in different orbital paths around the earth. The particle types, interaction mechanisms and damage nomenclature are described. Proton irradiation experiments to analyze worst case displacement and ionization damage are examined in chapter III. A description of the test conditions is first presented, followed by the experimental results on the observed dc and ac transistor performance metrics with incident radiation. The impact of the collector doping level on the degradation is discussed. In a similar fashion, gamma irradiation experiments to focus on ionization only effects are presented in chapter IV. The experimental design and dc results are first presented, followed by a comparison of degradation under proton irradiation. Additional proton dose rate experiments conducted to further investigate observed differences between proton and gamma results are presented.

The object of this thesis is to explore the low-frequency noise (LFN) in silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) and lateral bipolar junction transistors (BJTs). The LFN of SiGe HBTs and lateral BJTs not only determines the lowest detectable signal limit but also induces phase noise in high-frequency applications. Characterizing the LFN behavior and understanding the physical noise mechanism, therefore, are very important to improve the device and circuit performance. The dissertation achieves the object by investigating the LFN of SiGe HBTs and lateral BJTs with different structures for performance optimization and radiation tolerance, as well as by building models that explain the physical mechanism of LFN in these advance bipolar technologies. The scope of this research is separated into two main parts: the LFN of SiGe HBTs; and the LFN of lateral BJTs. The research in the LFN of SiGe HBTs includes investigating the effects of interfacial oxide (IFO), temperature, geometrical dimensions, and proton radiation. It also includes utilizing physical models to probe noise mechanisms. The research in the LFN of lateral BJTs includes exploring the effects of doping and geometrical dimensions. The research work is envisioned to enhance the understanding of LFN in SiGe HBTs and lateral BJTs.