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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
11

Storage-Aware Test Sets for Defect Detection and Diagnosis

Hari Narayana Addepalli (18276325) 03 April 2024 (has links)
<p dir="ltr">Technological advancements in the semiconductor industry have led to the development of fast, low-power, and high-performance electronic devices. With evolving process technologies, the size of an electronic device has greatly reduced, and the number of features a single device can support has steadily increased. To achieve this, billions of transistors are integrated into small electronic chips leading to an increase in the complexity of manufacturing processes. Electronic chips that are manufactured using such complex manufacturing processes are prone to have a large number of defects that are difficult to test, and cause reliability issues. To tackle these issues and produce highly reliable chips, there is a growing need to test each manufactured chip thoroughly. This requires the application of a large number of tests by a tester. The cost of testing an electronic chip primarily depends on the storage requirements of the tester, and the test application time required. The large number of tests required to rigorously test each chip leads to an increase in the testing cost. Earlier works reduced the testing cost by reducing the input storage requirements of the tester. The input storage requirements are reduced by using each stored test on the tester to apply several different tests to the circuit. Several different tests are also applied based on each stored test to improve the quality of a test set. The goal of this thesis is to aide in producing reliable chips, by creating test sets that can detect faults from different fault models. The test sets are created by improving the quality of a test set. </p><p><br></p><p dir="ltr">First, test sets with low storage requirements are produced for defect detection. A base test set is generated and stored. Each stored test is perturbed to produce several different tests. Algorithms are then described in two different scenarios to select a subset of the perturbed tests. The selected subset of tests improves the quality of defect detection with a minimal increase in the input storage requirements.</p><p><br></p><p dir="ltr">Next, test sets with low-storage requirements are produced for defect diagnosis. A fault detection test set is generated and stored. Each stored test is perturbed to produce several different tests. A procedure is then described to select a subset of the perturbed tests to be used as diagnostic tests. The diagnostic test set selected improves the quality of defect diagnosis with a minimal increase in the input storage requirements.</p><p><br></p><p dir="ltr">Finally, storage-aware test sets are produced targeting several fault models in two steps. In the first step, tests in a base test set are replaced with improved tests to produce an improved test set. The improved test set is stored, and it improves the quality of defect detection with no increase in the storage requirements. In the second step, each improved test is perturbed to produce several different tests. A procedure is then described to select a subset of the perturbed tests. The selected subset of tests further improves the quality of defect detection with a minimal increase in the input storage requirements.</p>
12

CMOS Integrated Resonators and Emerging Materials for MEMS Applications

Jackson Anderson (16551828) 18 July 2023 (has links)
<p>With the advent of increasingly complex radio systems at higher frequencies and the slowing of traditional CMOS process scaling with power concerns, there has been an increased focus on integration, architectural, and material innovations as a continued path forward in MEMS and logic. This work presents the first comprehensive experimental study of resonant body transistors in a commercial 14nm FinFET process, demonstrating differential radio frequency transduction as a function of transistor biasing through electrostatic, piezoresistive, and threshold voltage modulation. The impact of device design changes on unreleased resonator performance are further explored, highlighting the importance of phononic confinement in achieving an f*Q product of 8.2*10<sup>11</sup> at 11.73 GHz. Also shown are initial efforts towards the understanding of coupled oscillator architectures and a perovskite nickelate material system. Finally, development of resonators based on two-dimensional materials, whose scale is particularly attractive for high-frequency nano-mechanical resonators and acoustic devices, is discussed. Experiments towards dry transfer of tellurene flakes using geometries printed via two photon polymerization are presented along with optimization of a fabrication process for gated RF devices, presenting new opportunities for high-frequency electro-mechanical interactions in this topological material. </p>
13

Advanced Electrical Analysis of Low Noise MOSFET and Circuit Implementation for Low Power RFID Application

Nathan J Conrad (18494457) 06 May 2024 (has links)
<p dir="ltr">Semiconductor technology has propelled human society into the information age, and that progress continues. Silicon CMOS device has been aggressively scaled down to 5 nm technology node. To further boost the on-state performance, MOS technology based on high-mobility channels such as III-V and Ge have been intensively studied. 3D structures such as FinFETs and gate-all-around (GAA) FETs are also applied to III-V and Ge to improve the electrostatic control of the channels for the ultimate scaling. </p><p><br></p><p dir="ltr">Traditional semiconductor device characterization techniques are inapplicable to devices created through these novel materials and device structures. This work applies various techniques to characterize a wide variety of semiconductor devices, in addition to presenting novel techniques studying the reliability of commercial off the shelf (COTS) products. Finally, the design of an ultra-low-power RF ASIC implementing wireless neural recording and stimulation, designed for cranial implantation, will be presented.</p>
14

Effect of the voltage dependency of the device-level gate-source capacitance in the linearity of a common-gate amplifier

Eduardo A. Garcia (5929682) 19 July 2022 (has links)
<p>Most work on amplifier linearity has focused on the transconductance (gm) linearity, but there is increasing evidence that the voltage-dependence of the gate-source capacitance (Cgs) plays an important role in the linearity of emerging devices. This work addresses the capacitance contribution by incorporating the nonlinearities attributed to the voltage dependency of Cgs of a general FET on a circuit-level Cg amplifier model.</p> <p>An amplifier model including a voltage-dependent Cgs, and a voltage-dependent gm is studied using harmonic analysis and Volterra series. A closed form expression for the  third-order intercept point (IP3) of the amplifier, which depends on the nonlinear coefficients of Cgs, is obtained. A simple design rule, and a formula for the reduction of the IP3 due to the voltage-dependent Cgs are also presented. </p> <p>As application examples, the linearity of an amplifier based on a specific device is analyzed for two cases by extracting the nonlinear circuit parameters of the device. First for an analytic model of a bulk mosfet. Second for a one-dimensional, ballistic, coaxially gated Si nanowire. For low frequencies of design, the distortion introduced by gm is predominant, but for high frequencies it is obscured by the distortion coming from Cgs.</p> <p>We conclude that taking into account the voltage-dependence of Cgs is crucial when predicting the linearity behavior of a Cg amplifier, either designed for high-frequency operation, or based on a device operating near the quantum capacitance limit. </p>
15

AN ORGANIC NEURAL CIRCUIT: TOWARDS FLEXIBLE AND BIOCOMPATIBLE ORGANIC NEUROMORPHIC PROCESSING

Mohammad Javad Mirshojaeian Hosseini (16700631) 31 July 2023 (has links)
<p>Neuromorphic computing endeavors to develop computational systems capable of emulating the brain’s capacity to execute intricate tasks concurrently and with remarkable energy efficiency. By utilizing new bioinspired computing architectures, these systems have the potential to revolutionize high-performance computing and enable local, low-energy computing for sensors and robots. Organic and soft materials are particularly attractive for neuromorphic computing as they offer biocompatibility, low-energy switching, and excellent tunability at a relatively low cost. Additionally, organic materials provide physical flexibility, large-area fabrication, and printability.</p><p>This doctoral dissertation showcases the research conducted in fabricating a comprehensive spiking organic neuron, which serves as the fundamental constituent of a circuit system for neuromorphic computing. The major contribution of this dissertation is the development of the organic, flexible neuron composed of spiking synapses and somas utilizing ultra-low voltage organic field-effect transistors (OFETs) for information processing. The synaptic and somatic circuits are implemented using physically flexible and biocompatible organic electronics necessary to realize the Polymer Neuromorphic Circuitry. An Axon-Hillock (AH) somatic circuit was fabricated and analyzed, followed by the adaptation of a log-domain integrator (LDI) synaptic circuit and the fabrication and analysis of a differential-pair integrator (DPI). Finally, a spiking organic neuron was formed by combining two LDI synaptic circuits and one AH synaptic circuit, and its characteristics were thoroughly examined. This is the first demonstration of the fabrication of an entire neuron using solid-state organic materials over a flexible substrate with integrated complementary OFETs and capacitors.</p>
16

ENERGY-EFFICIENT SENSING AND COMMUNICATION FOR SECURE INTERNET OF BODIES (IOB)

Baibhab Chatterjee (9524162) 28 July 2022 (has links)
<p>The last few decades have witnessed unprecedented growth in multiple areas of electronics spanning low-power sensing, intelligent computing and high-speed wireless connectivity. In the foreseeable future, there would be hundreds of billions of computing devices, sensors, things and people, wherein the technology will become intertwined with our lives through continuous interaction and collaboration between humans and machines. Such human-centric ideas give rise to the concept of internet of bodies (IoB), which calls for novel and energy-efficient techniques for sensing, processing and secure communication for resource-constrained IoB nodes.As we have painfully learnt during the pandemic, point-of-care diagnostics along with continuous sensing and long-term connectivity has become one of the major requirements in the healthcare industry, further emphasizing the need for energy-efficiency and security in the resource-constrained devices around us.</p> <p>  </p> <p>  With this vision in mind, I’ll divide this dissertation into the following chapters. The first part (Chapter 2) will cover time-domain sensing techniques which allow inherent energy-resolution scalability, and will show the fundamental limits of achievable resolution. Implementations will include 1) a radiation sensing system for occupational dosimetry in healthcare and mining applications, which can achieve 12-18 bit resolution with 0.01-1 µJ energy dissipation, and 2) an ADC-less neural signal acquisition system with direct Analog to Time Conversion at 13pJ/Sample. The second part (Chapters 3 and 4) of this dissertation will involve the fundamentals of developing secure energy-efficient electro-quasistatic (EQS) communication techniques for IoB wearables as well as implants, and will demonstrate  2 examples: 1) Adiabatic Switching for breaking the αCV^2f limit of power consumption in capacitive voltage mode human-body communication (HBC), and 2) Bi-Phasic Quasistatic Brain Communication (BP-QBC) for fully wireless data transfer from a sub-6mm^3, 2 µW brain implant. A custom modulation scheme, along with adiabatic communication enables wireline-like energy efficiencies (<5pJ/b) in HBC-based wireless systems, while the BP-QBC node, being fully electrical in nature, demonstrates sub-50pJ/b efficiencies by eliminating DC power consumption, and by avoiding the transduction losses observed in competing technologies, involving optical, ultrasound and magneto-electric modalities. Next in Chapter 5, we will show an implementation of a reconfigurable system that would include 1) a human-body communication transceiver and 2) a traditional wireless (MedRadio) transceiver on the same integrated circuit (IC), and would demonstrate methods to switch between the two modes by detecting the placement of the transmitter and receiver devices (on-body/away from the body). Finally, in Chapter 6, we shall show a technique of augmenting security in resource-constrained devices through authentication using the Analog/RF properties of the transmitter, which are usually discarded as non-idealities in a digital transceiver chain. This method does not require any additional hardware in the transmitter, making it an extremely promising technique to augment security in highly resource-constrained scenarios. Such energy-efficient intelligent sensing and secure communication techniques, when combined with intelligent in-sensor-analytics at the resource-constrained nodes, can potentially pave the way for perpetual, and even batteryless systems for next-generation IoT, IoB and healthcare applications.</p>
17

IIoT-based Instrumentation and Control System for a Lateral Micro-drilling Robot Using Machine Fault Diagnosis and Failure Prognosis

Jose A. Solorio Cervantes (11191893) 11 October 2023 (has links)
<p dir="ltr">This project aimed to develop an instrumentation and control system for a micro-drilling robot based on Industrial Internet of Things (IIoT) technologies. The automation system integrated IIoT technological tools to create a robust automation system capable of being used in drilling operations. The system incorporated industrial-grade sensors, which carried out direct measurements of the critical variables of the process. The indirect variables relevant to the control of the robot were calculated from the measured parameters. The system also considered the telemetry architecture necessary to reliably transmit data from the down-the-hole (DTH) robot to a receiver on the surface. Telemetry was based on wireless communication through long-range radio frequency (LoRa). The system developed had models based on Artificial Intelligence (AI) and Machine Learning (ML) for determining the mode of operation, detecting changes in the process, and changes in drilling variables in critical hydraulic components for the drilling process. Algorithms based on AI and ML models also allowed the user to make better decisions based on the variables' correlation to optimize the drilling process (e.g., dynamic change of flow, pressure, and RPMs based on automatic rock identification). A user interface (UI) was developed, and digital tools to perform data analysis were implemented. Safety assessment in all robot systems (e.g., electrical, hardware, software) was contemplated as a critical design component. The result of this research project provides innovative micro-drilling robots with the necessary technological tools to optimize the drilling process. The system made drilling more efficient, reliable, and safe, providing diagnostic and prognostic tools that allowed planning maintenance based on the actual health of the devices. The system that was developed was tested in a test bench under controlled conditions within a laboratory to characterize the system and collect data that allowed ML models' development, training, validation, and testing. The prototype of a micro-drilling robot installed on the test bench served as a case study to assess the implemented models' reliability and the proposed telemetry.</p>

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