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Thesis (Ph. D.)--University of Texas at Austin, 2008. / Vita. Includes bibliographical references and index.

Thesis (Ph. D.)--Lehigh University, 2004. / Includes vita. Includes bibliographical references (leaves 256-263).

<p dir="ltr">The intricate domain of chip design encompasses the creation of intricate blueprints for integrated circuits (ICs). Algorithms, pivotal in this realm, assume the role of optimizing IC performance and functionality. This thesis delves into the utilization of algorithms within chip design, spotlighting their potential to amplify design process efficiency and efficacy. Notably, this study undertakes a comprehensive comparison of algorithmic performances on both Central Processing Units (CPUs) and Graphics Processing Units (GPUs). A cornerstone application of algorithms in chip design lies in logic synthesis, which transmutes a high-level circuit description into a silicon-compatible, low-level representation. By minimizing gate requisites, curtailing power consumption, and bolstering performance, algorithms serve as architects of optimized logic synthesis. Furthermore, the arena of physical design harnesses algorithms to translate logical designs into physically realizable layouts on silicon wafers. This involves meticulous considerations like routing congestion and power efficiency. Furthermore, this thesis adopts a thorough approach by extensively exploring the implementation intricacies of two pivotal physical design algorithms. The Kernighan-Lin Partitioning Algorithm is prominently featured for optimizing Placement and Partitioning, while Lee’s Algorithm provides valuable insights for enhancing Routing. Through a meticulous comparison of dataset efficiency and run-time across both hardware platforms, noteworthy insights have emerged. In KL Algorithm, datasets categorized as small (with sizes < 105), the CPU demonstrates a 1.2X faster processing speed compared to the GPU. However, as dataset sizes surpass this threshold, a distinct trend emerges: while GPU run times remain relatively consistent, CPU run times undergo a threefold increase at select points. In the case of Lee’s Algorithm, the CPU demonstrated superior execution time despite having fewer cores and threads than the GPU. This can be attributed to the inherently sequential nature of Lee’s Algorithm, where each element depends on the preceding one, aligning with the CPU's strength in handling sequential tasks. This thesis embarks on a comprehensive analytical journey, delving into the nuanced interplay between these contrasting aspects.</p>

Thesis (Ph. D.)--Oregon State University, 2008. / Printout. Includes bibliographical references (leaves 103-110). Also available on the World Wide Web.

Thesis (M.App.Sc.) - Carleton University, 2005. / Includes bibliographical references (p. 161-165). Also available in electronic format on the Internet.

Thesis (Ph.D.) - Carleton University, 2006. / Includes bibliographical references (p. 203-216). Also available in electronic format on the Internet.

<p> With the increased use of the internet, artificial intelligence, IoT, and wearable devices, it has become significantly critical to ensure security and confidentiality of information, particularly within these resource-constrained edge devices. The increased attentions to security and confidentially of information led to the development of computationally-secure cryptographic algorithms. At the same time, low-power sensing devices have emerged as highly promising tools for a wide range of technological applications such as diagnostics, physiological monitoring, and healthcare systems. The desire for seamless and continuous monitoring in sensing applications necessitates these devices to be compact in size and exhibit low power consumption, making them suitable for wearable or portable use with batterypowered operation.</p> <p> Keeping this objective in focus, I will structure this dissertation into the subsequent chapters. The first part (Chapter 2) will cover a theoretical analysis of the proposed Co-planar capacitivE Asymmetry SEnsing (CEASE) technique utilizing four on-die top-layer metal plates. Also, it will present the comparison with other sensing methods which are capacitive parallel and inductive sensing technique in terms of detection range through electromagnetic simulation. The second part (Chapters 3) of this this dissertation will involve explore of the concept of capacitive sensing in an IC layout and co-optimizing both the ground plane capacitance and the sensing capacitance to maximize sensitivity. It will present design of the post-processing circuits and systems with ultra-low power for sensing attacks and to prove the efficacy through the post-layout simulation results. Additionally, integration with digital SCA protection and AES-256 crypto core and checking the efficacy of the proposed method using the integrated detection and countermeasure system in post-layout simulations. Next in Chapter 4, we will show the lowest-power and the energy/conversion step time-based RDC for low frequency applications. It will presents the ways to enhance the energy-resolution trade-offs in time-based RDC, improving the rms jitter/phase noise with help of speed-up latches, to achieve higher bit-resolution. Furthermore, the power/performance trade-off in experiment through 3 different design variations optimized towards lowest energy baseline, higher resolution, and process portability tapeout and IC measurements is presented. Finally, in Chapter 5, we will show a novel proposed switchable dual-mode device that combines a high-frequency antenna and a Human Body Communication (HBC) coupler in a single device. The integration of these two modes addresses the limitations of HBC, such as restricted data transmission, and overcomes the drawbacks of signal absorption in the 24GHz frequency band by the human body. </p>

<p>Gastroparesis and functional dyspepsia are debilitating stomach disorders that together affect 10% of the world population. Modulating gastric function is an important target function for alternative therapies like gastric electrical stimulation (GES). The Enterra device is the only FDA approved implantable device currently available that can administer GES to entrain gastric slow wave activity. However, recent evidence has called into question the clinical utility of this system. In this work, I present the development and in vivo application of a new, closed loop, chronically implantable electroceutical device capable of continuously recording gastric motility and administering synchronous GES, that will form the needed foundation for neuromodulation protocols that can correct shortcomings in past, first-generation bioelectronic attempts to ameliorate and monitor gastric disorders. This system captures gastric serosal myoelectric activity using electrogastrography, as well as gastric contraction activity using strain gauge force transducers. I present data captured from anesthetized and freely behaving rats, demonstrating the ability of the device to capture physiologically relevant gastric motility patterns and changes, safely and effectively. I present a framework built on continuous wavelet transforms to analyze frequency and amplitude changes in captured data to inform potential therapies. I present data demonstrating the ability of the device to selectively stimulate enteric neurons in sync with gastric slow waves, resulting in a relaxation of the pyloric sphincter muscle, in a closed loop fashion. I present the development of a large animal preclinical proof-of-principle version of this system, and data captured from its implantation in freely behaving pigs, as a translational step to future human trials. In the future, this system will enable further studies into future closed loop therapies aimed at increasing gastric accommodation, stimulating physiological gastric emptying and/or pyloric opening with physiologically appropriate timing and extent. </p>

<p dir="ltr">Technological advancements in the semiconductor industry have led to the development of fast, low-power, and high-performance electronic devices. With evolving process technologies, the size of an electronic device has greatly reduced, and the number of features a single device can support has steadily increased. To achieve this, billions of transistors are integrated into small electronic chips leading to an increase in the complexity of manufacturing processes. Electronic chips that are manufactured using such complex manufacturing processes are prone to have a large number of defects that are difficult to test, and cause reliability issues. To tackle these issues and produce highly reliable chips, there is a growing need to test each manufactured chip thoroughly. This requires the application of a large number of tests by a tester. The cost of testing an electronic chip primarily depends on the storage requirements of the tester, and the test application time required. The large number of tests required to rigorously test each chip leads to an increase in the testing cost. Earlier works reduced the testing cost by reducing the input storage requirements of the tester. The input storage requirements are reduced by using each stored test on the tester to apply several different tests to the circuit. Several different tests are also applied based on each stored test to improve the quality of a test set. The goal of this thesis is to aide in producing reliable chips, by creating test sets that can detect faults from different fault models. The test sets are created by improving the quality of a test set. </p><p><br></p><p dir="ltr">First, test sets with low storage requirements are produced for defect detection. A base test set is generated and stored. Each stored test is perturbed to produce several different tests. Algorithms are then described in two different scenarios to select a subset of the perturbed tests. The selected subset of tests improves the quality of defect detection with a minimal increase in the input storage requirements.</p><p><br></p><p dir="ltr">Next, test sets with low-storage requirements are produced for defect diagnosis. A fault detection test set is generated and stored. Each stored test is perturbed to produce several different tests. A procedure is then described to select a subset of the perturbed tests to be used as diagnostic tests. The diagnostic test set selected improves the quality of defect diagnosis with a minimal increase in the input storage requirements.</p><p><br></p><p dir="ltr">Finally, storage-aware test sets are produced targeting several fault models in two steps. In the first step, tests in a base test set are replaced with improved tests to produce an improved test set. The improved test set is stored, and it improves the quality of defect detection with no increase in the storage requirements. In the second step, each improved test is perturbed to produce several different tests. A procedure is then described to select a subset of the perturbed tests. The selected subset of tests further improves the quality of defect detection with a minimal increase in the input storage requirements.</p>