<p> With the increased use of the internet, artificial intelligence, IoT, and wearable devices, it has become significantly critical to ensure security and confidentiality of information, particularly within these resource-constrained edge devices. The increased attentions to security and confidentially of information led to the development of computationally-secure cryptographic algorithms. At the same time, low-power sensing devices have emerged as highly promising tools for a wide range of technological applications such as diagnostics, physiological monitoring, and healthcare systems. The desire for seamless and continuous monitoring in sensing applications necessitates these devices to be compact in size and exhibit low power consumption, making them suitable for wearable or portable use with batterypowered operation.</p> <p> Keeping this objective in focus, I will structure this dissertation into the subsequent chapters. The first part (Chapter 2) will cover a theoretical analysis of the proposed Co-planar capacitivE Asymmetry SEnsing (CEASE) technique utilizing four on-die top-layer metal plates. Also, it will present the comparison with other sensing methods which are capacitive parallel and inductive sensing technique in terms of detection range through electromagnetic simulation. The second part (Chapters 3) of this this dissertation will involve explore of the concept of capacitive sensing in an IC layout and co-optimizing both the ground plane capacitance and the sensing capacitance to maximize sensitivity. It will present design of the post-processing circuits and systems with ultra-low power for sensing attacks and to prove the efficacy through the post-layout simulation results. Additionally, integration with digital SCA protection and AES-256 crypto core and checking the efficacy of the proposed method using the integrated detection and countermeasure system in post-layout simulations. Next in Chapter 4, we will show the lowest-power and the energy/conversion step time-based RDC for low frequency applications. It will presents the ways to enhance the energy-resolution trade-offs in time-based RDC, improving the rms jitter/phase noise with help of speed-up latches, to achieve higher bit-resolution. Furthermore, the power/performance trade-off in experiment through 3 different design variations optimized towards lowest energy baseline, higher resolution, and process portability tapeout and IC measurements is presented. Finally, in Chapter 5, we will show a novel proposed switchable dual-mode device that combines a high-frequency antenna and a Human Body Communication (HBC) coupler in a single device. The integration of these two modes addresses the limitations of HBC, such as restricted data transmission, and overcomes the drawbacks of signal absorption in the 24GHz frequency band by the human body. </p>

<div>The huge gamut of today’s internet-connected embedded devices has led to increasing concerns regarding the security and confidentiality of data. To address these requirements, most embedded devices employ cryptographic algorithms, which are computationally secure. Despite such mathematical guarantees, as these algorithms are implemented on a physical platform, they leak critical information in the form of power consumption, electromagnetic (EM) radiation, timing, cache hits and misses, and so on, leading to side-channel analysis (SCA) attacks. Non-profiled SCA attacks like differential/correlational power/EM analysis (DPA/CPA/DEMA/CEMA) are direct attacks on a single device to extract the secret key of an encryption algorithm. On the other hand, profiled attacks comprise of building an offline template (model) using an identical device and the attack is performed on a similar device with much fewer traces.</div><div><br></div><div>This thesis focusses on developing efficient side-channel attacks and circuit-level low-overhead generic countermeasures. A cross-device deep learning-based profiling power side-channel attack (X-DeepSCA) is proposed which can break the secret key of an AES-128 encryption engine running on an Atmel microcontroller using just a single power trace, thereby increasing the threat surface of embedded devices significantly. Despite all these advancements, most works till date, both attacks as well as countermeasures, treat the crypto engine as a black box, and hence most protection techniques incur high power/area overheads.</div><div><br></div><div>This work presents the first white-box modeling of the EM leakage from a crypto hardware, leading to the understanding that the critical correlated current signature should not be passed through the higher metal layers. To achieve this goal, a signature attenuation hardware (SAH) is utilized, embedding the crypto core locally within the lower metal layers so that the critical correlated current signature is not passed through the higher metals, which behave as efficient antennas and its radiation can be picked up by a nearby attacker. Combination of the 2 techniques – current-domain signature suppression and local lower metal routing shows >350x signature attenuation in measurements on our fabricated 65nm test chip, leading to SCA resiliency beyond 1B encryptions, which is a 100x improvement in both EM and power SCA protection over the prior works with comparable overheads. Moreover, this is a generic countermeasure and can be utilized for any crypto core without any performance degradation.</div><div><br></div><div>Next, backed by our physics-level understanding of EM radiation, a digital library cell layout technique is proposed which shows >5x reduction in EM SCA leakage compared to the traditional digital logic gate layout design. Further, exploiting the magneto-quasistatic (MQS) regime of operation for the present-day CMOS circuits, a HFSS-based framework is proposed to develop a pre-silicon EM SCA evaluation technique to test the vulnerability of cryptographic implementations against such attacks during the design phase itself.</div><div><br></div><div>Finally, considering the continuous growth of wearable and implantable devices around a human body, this thesis also analyzes the security of the internet-of-body (IoB) and proposes electro-quasistatic human body communication (EQS-HBC) to form a covert body area network. While the traditional wireless body area network (WBAN) signals can be intercepted even at a distance of 5m, the EQS-HBC signals can be detected only up to 0.15m, which is practically in physical contact with the person. Thus, this pioneering work proposing EQS-HBC promises >30x improvement in private space compared to the traditional WBAN, enhancing physical security. In the long run, EQS-HBC can potentially enable several applications in the domain of connected healthcare, electroceuticals, augmented and virtual reality, and so on. In addition to these physical security guarantees, side-channel secure cryptographic algorithms can be augmented to develop a fully secure EQS-HBC node.</div>