<p><a>Low reflow temperature solder interconnect technology based on Sn-Bi alloys is currently being considered as an alternative for Sn-Ag-Cu solder alloys to form solder interconnects at significantly lower melting temperatures than required for Sn-Ag-Cu alloys. </a></p> <p>A new low temperature interconnect technology based on Sn-Bi alloys is being considered for attaching Sn-Ag-Cu (SAC) solder BGAs to circuit boards at temperatures significantly lower than for homogeneous SAC joints. Microstructure development studies of reflow and annealing, including Bi diffusion and precipitation, are important in understanding mechanical reliability and failures paths in the resulting heterogeneous joints. Experiments in several SAC-SnBi geometries revealed that Bi concentration profiles deviate from local equilibrium expected from the phase diagram, with much higher local concentrations and lower volume fractions of liquid than expected during short-time high temperature anneals in the two-phase region. As annealing time increased and Sn grain coarsening occurred, the compositions and fractions revert to the phase diagram, suggesting an “anti-Scheil” effect. A Bi interface segregation model based on Bi segregation at Sn grain boundaries was developed to explain the Bi distribution characteristics in Sn during two-phase annealing process. </p> <p>Besides hybrid joints, microstructural evolution after reflow and aging, especially of intermetallic compound (IMC) growth at solder/pad surface finish interfaces in homogeneous SnBi LTS joints, is also important to understanding fatigue life and crack paths in the solder joints. This study describes intermetallic growth in homogeneous solder joints of Sn-Bi eutectic alloy and Sn-Bi-Ag alloys formed with electroless nickel-immersion gold (ENIG) and Cu-organic surface protection (Cu-OSP) surface finishes. Experimental observations revealed that, during solid state annealing following reflow, the 50nm Au from the ENIG surface finish catalyzed rapid (Au,Ni)Sn₄ intermetallic growth at the Ni-solder interface in both Sn-Bi and Sn-Bi-Ag homogeneous joints, which led to significant solder joint embrittlement during fatigue testing. Further study found that the growth rate of (Au,Ni)Sn₄ intermetallic could be reduced by In and Sb alloying of SnBi solders and is totally eliminated with Cu addition. Fatigue testing revealed Au embrittlement is always present in solder joints without Cu, even with In and Sb additions due to (Au,Ni)Sn₄ formation. The fatigue reliability of Cu-containing alloys is better on ENIG due to the formation of (Ni,Cu,Au)₆Sn₅ at the solder-surface finish interface instead of (Au,Ni)Sn₄.</p> <p>With the development of SnBi LTSs, a new generation alloy called HRL1 stands out for its outstanding reliability during thermal cycling and drop shock testing. This study focused on microstructure evolution in SnBi eutectic, SnBiAg eutectic and HRL1 solders (MacDermid Alpha) homogeneous joints and hybrid joints with SAC305 formed with ENIG and Cu-OSP surface finishes. Experimental results revealed that with more microalloying elements, HRL1 has significantly refined microstructure and slower Sn grain growth rate during solid-state aging compared with SnBi and SnBiAg eutectic alloys. Intermetallic compound growth study showed that during solid state annealing following reflow, the (50nm) Au from the ENIG finish catalyzed rapid (Au,Ni)Sn₄ intermetallic growth at the Ni-solder interface in both Sn-Bi and Sn-Bi-Ag homogeneous joints, which led to significant solder joint embrittlement during creep and fatigue loading. However, (Au,Ni)Sn₄ growth and gold embrittlement was completely eliminated for HRL1 due to Cu additions in it, and HRL1 has significantly better fatigue reliability than SnBi and SnBiAg eutectic alloys on both OSP and ENIG surface finishes.</p>

In this thesis, we have proposed a new computing platform called probabilistic spin logic (PSL) based on probabilistic bits (p-bit) using low barrier nanomagnets (LBM) whose thermal barrier is of the order of a kT unlike conventional memory and spin logic devices that rely on high thermal barrier magnets (40-60 kT) to retain stability. p-bits are tunable random number generators (TRNG) analogous to the concept of binary stochastic neurons (BSN) in artificial neural network (ANN) whose output fluctuates between a +1 and -1 states with 50-50 probability at zero input bias and the stochastic output can be tuned by an applied input producing a sigmoidal characteristic response. p-bits can be interconnected by a synapse or weight matrix [J] to build p-circuits for solving a wide variety of complex unconventional problems such as inference, invertible Boolean logic, sampling and optimization. It is important to update the p-bits sequentially for proper operation where each p-bit update is informed of the states of other p-bits that it is connected to and this requires the use of sequencers in digital clocked hardware. But the unique feature of our probabilistic hardware is that they are autonomous that runs without any clocks or sequencers.<br>To ensure the necessary sequential informed update in our autonomous hardware it is important that the synapse delay is much smaller than the neuron fluctuation time.<br>We have demonstrated the notion of this autonomous hardware by SPICE simulation of different designs of low barrier nanomagnet based p-circuits for both symmetrically connected Boltzmann networks and directed acyclic Bayesian networks. It is interesting to note that for Bayesian networks a specific parent to child update order is important and requires specific design rule in the autonomous probabilistic hardware to naturally ensure the specific update order without any clocks. To address the issue of scalability of these autonomous hardware we have also proposed and benchmarked compact models for two different hardware designs against SPICE simulation and have shown that the compact models faithfully mimic the dynamics of the real hardware.<br>

<p>Conventional computing is based on the concept of bits which are classical entities that are either 0 or 1 and can be represented by stable magnets. The field of quantum computing relies on qubits which are a complex linear combination of 0 and 1. Recently, the concept of probabilistic computing with probabilistic (<em>p-</em>)bits was introduced where <em>p-</em>bits are robust classical entities that fluctuate between 0 and 1. <em>P-</em>bits can be naturally represented by low-barrier nanomagnets. Probabilistic computers (<em>p-</em>computers) based on <em>p-</em>bits are domain-based hardware accelerators for Monte Carlo algorithms that can efficiently address probabilistic tasks like sampling, optimization and machine learning. </p> <p>In this dissertation, starting from the intrinsic physics of nanomagnets, we show that a compact hardware implementation of a <em>p-</em>bit based on stochastic magnetic tunnel junctions (s-MTJs) can operate at high-speeds in the order of nanoseconds, a prediction that has recently received experimental support.</p> <p>We then move to the system level and illustrate by simulation and by experiment how multiple interconnected <em>p-</em>bits can be utilized to train a Boltzmann machine built with hardware <em>p-</em>bits. We observe that even non-ideal s-MTJs can be utilized for probabilistic computing when combined with hardware-aware learning.</p> <p>Finally, we show how to build a <em>p-</em>computer to accelerate a wide variety of problems ranging from optimization and sampling to quantum computing and machine learning. The common theme for all these applications is the underlying Monte Carlo and Markov chain Monte Carlo algorithms and their parallelism enabled by a unique <em>p-</em>computer architecture.</p>

<p>With the Moore’s Law era coming to an end, much attention has been given to novel nanoelectronic devices as a key driving force behind technological innovation. Utilizing the inherent device physics of nanoelectronic components, for sensory and computational tasks have proven to be useful in reducing the area and energy requirements of the underlying hardware fabrics. In this work we demonstrate how the intrinsic noise present in nano magnetic devices can pave the pathway for energy efficient neuromorphic hardware. Furthermore, we illustrate how the unique magnetic properties of such devices can be leveraged for accurate estimation of environmental magnetic fields. We focus on spintronic technologies in particular, due to the low current and energy requirements in contrast to traditional CMOS technologies.</p><p>Image segmentation is a crucial pre-processing stage used in many object identification tasks that involves simplifying the representation of an image so it can be conveniently analyzed in the later stages of a problem. This is achieved through partitioning a complicated image into specific groups based on color, intensity or texture of the pixels of that image. Locally Excitatory Globally Inhibitory Oscillator Network or LEGION is one such segmentation algorithm, where synchronization and desynchronization between coupled oscillators are used for segmenting an image. In this work we present an energy efficient and scalable hardware implementation of LEGION using stochastic Magnetic Tunnel Junctions that leverage the fast parallel</p><p> nature of the algorithm. We demonstrate that the proposed hardware is capable of segmenting binary and gray-scale images with multiple objects more efficiently than<br> existing hardware implementations. </p><p>It is understood that the underlying device physics of spin devices can be used for emulating the functionality of a spiking neuron. Stochastic spiking neural networks based on nanoelectronic spin devices can be a possible pathway of achieving brain-like compact and energy-efficient cognitive intelligence. Current computational models attempt to exploit the intrinsic device stochasticity of nanoelectronic synaptic or neural components to perform learning and inference. However, there has been limited analysis on the scaling effect of stochastic spin devices and its impact on the operation of such stochastic networks at the system level. Our work attempts to explore the design space and analyze the performance of nanomagnet based stochastic neuromorphic computing architectures, for magnets with different barrier heights. We illustrate how the underlying network architecture must be modified to account for the random telegraphic switching behavior displayed by magnets as they are scaled into the superparamagnetic regime.<br></p><p>Next we investigate how the magnetic properties of spin devices can be utilized for real world sensory applications. Magnetic Tunnel Junctions can efficiently translate variations in external magnetic fields into variations in electrical resistance. We couple this property of Magnetic Tunnel Junctions with Amperes law to design a non-invasive sensor to measure the current flowing through a wire. We demonstrate how undesirable effects of thermal noise and process variations can be suppressed through novel analog and digital signal conditioning techniques to obtain reliable and accurate current measurements. Our results substantiate that the proposed noninvasive current sensor surpass other state-of-the-art technologies in terms of noise and accuracy.<br></p><br>

<div><p>Analyzing behaviors of objects on the road is a complex task that requires data from various sensors and their fusion to recreate movement of objects with a high degree of accuracy. A data collection and processing system are thus needed to track the objects accurately in order to make an accurate and clear map of the trajectories of objects relative to various coordinate frame(s) of interest in the map. Detection and tracking moving objects (DATMO) and Simultaneous localization and mapping (SLAM) are the tasks that needs to be achieved in conjunction to create a clear map of the road comprising of the moving and static objects.</p> <p> These computational problems are commonly solved and used to aid scenario reconstruction for the objects of interest. The tracking of objects can be done in various ways, utilizing sensors such as monocular or stereo cameras, Light Detection and Ranging (LIDAR) sensors as well as Inertial Navigation systems (INS) systems. One relatively common method for solving DATMO and SLAM involves utilizing a 3D LIDAR with multiple monocular cameras in conjunction with an inertial measurement unit (IMU) allows for redundancies to maintain object classification and tracking with the help of sensor fusion in cases when sensor specific traditional algorithms prove to be ineffectual when either sensor falls short due to their limitations. The usage of the IMU and sensor fusion methods relatively eliminates the need for having an expensive INS rig. Fusion of these sensors allows for more effectual tracking to utilize the maximum potential of each sensor while allowing for methods to increase perceptional accuracy. </p> <p>The focus of this thesis will be the dock-less e-scooter and the primary goal will be to track its movements effectively and accurately with respect to cars on the road and the world. Since it is relatively more common to observe a car on the road than e-scooters, we propose a data collection system that can be built on top of an e-scooter and an offline processing pipeline that can be used to collect data in order to understand the behaviors of the e-scooters themselves. In this thesis, we plan to explore a data collection system involving a 3D LIDAR sensor and multiple monocular cameras and an IMU on an e-scooter as well as an offline method for processing the data to generate data to aid scenario reconstruction. </p><br></div>

<div>A microheater and resistance temperature detector (RTD) are designed and fabricated for various applications. First, a hierarchical manifold microchannel heatsink with an integrated microheater and RTDs is demonstrated. Microfluidic cooling within the embedded heat sink improves heat dissipation, with two-phase operation offering the potential for dissipation of very high heat fluxes while maintaining moderate chip temperatures. To enable multi-chip stacking and other heterogeneous packaging approaches, it is important to densely integrate all fluid flow paths into the device. Therefore, the details of heatsink layouts and fabrication processes are introduced. Characterization of two-phase cooling as well as reliability of the microheater/RTDs are discussed. In addition, another application of microheater for mining particle detection using interdigitated capacitive sensor. While current personal monitoring devices are optimized for monitoring microscale particles, a higher resolution technique is required to detect sub-micron and nanoscale particulate matters (PM) due to smaller volume and mass of the particles. The detection capability of the capacitive sensor for sub-micron and nanoparticles are presented, and an incorporated microheater improved stable capacitive sensor reading under air flow and various humidity. </div><div>This paper also introduces the characterization of nanomaterials such as metallic nanowires (NWs) and single layer graphene. First, the copper nanowire (CuNW)/graphene hybrid networks for transparent conductors (TC) is investigated. Though indium tin oxide (ITO) has been widely used, demands for the next generation of TC is increasing due to a limited supply of indium. Thus, the optical and electrical properties of CuNW/graphene hybrid network are compared with other transparent conductive materials including ITO. Secondly, silver nanowire (AgNW) growth technique using electrodeposition is introduced. A vertically aligned branched AgNW arrays is made using a porous anodic alumina template and the optical properties of the structure are discussed.</div><div><br></div>

<div> <div> <div> <p>Transient liquid phase sintering (TLPS) technologies are potential low-temperature solders for sustainable replacements of lead-based solders and high-temperature lead-free solders. Compared to solid-state sintering and lead-free solders, TLPS uses lower temperatures and is, thus, suitable for assembling temperature-sensitive components. TLPS is a non- equilibrium process and determining the kinetics is critical to the estimation of processing times needed for good joining. The tin-indium (Sn-In) system with a eutectic temperature of 119°C is being considered as the basis for a TLPS system when combined with tin. Most models of TLPS include interdiffusion, dissolution, isothermal solidification, and homogenization and are based on simple binary alloys without intermediate phases. The Sn-In system has two intermediate phases and thus the reaction kinetics require additional terms in the modeling. Differential Scanning Calorimetry (DSC) has been used to measure the response of Sn-In alloys during the transient liquid phase reaction. Preparation of tin indium alloys for microstructural analysis is challenging due to their very low hardness. This study uses freeze-fracturing of the tin indium alloys to obtain sections for microstructural analysis. The combination of DSC and microstructure analysis provides information on the reaction kinetics. It was observed that the solid/liquid reaction does not proceed as quickly as desired, that is, substantial liquid remains after annealing even though the overall composition is in the single-phase region in the phase diagram. </p> </div> </div> </div>

<div> <div> <p>Phase transition materials (PTM) have garnered immense interest in concurrent post-CMOS electronics, due to their unique properties such as - electrically driven abrupt resistance switching, hysteresis, and high selectivity. The phase transitions can be attributed to diverse material-specific phenomena, including- correlated electrons, filamentary ion diffusion, and dimerization. In this research, we explore the application space for these materials through extensive device-circuit co-design and propose new ideas harnessing their unique electrical properties. The abrupt transitions and high selectivity of PTMs enable steep (< 60 mV/decade) switching characteristics in Hyper-FET, a promising post-CMOS transistor. We explore device-circuit co-design methodology for Hyper-FET and identify the criterion for material down-selection. We evaluate the achievable voltage swing, energy-delay trade-off, and noise response for this novel device. In addition to the application in low power logic device, PTMs can actively facilitate non-volatile memory design. We propose a PTM augmented Spin Transfer Torque (STT) MRAM that utilizes selective phase transitions to boost the sense margin and stability of stored data, simultaneously. We show that such selective transitions can also be used to improve other MRAM designs with separate read/write paths, avoiding the possibility of read-write conflicts. Further, we analyze the application of PTMs as selectors in cross-point memories. We establish a general simulation framework for cross-point memory array with PTM based <i>selector</i>. We explore the biasing constraints, develop detailed design methodology, and deduce figures of merit for PTM selectors. We also develop a computationally efficient compact model to estimate the leakage through the sneak paths in a cross-point array. Subsequently, we present a new sense amplifier design utilizing PTM, which offers built-in tunable reference with low power and area demand. Finally, we show that the hysteretic characteristics of unipolar PTMs can be utilized to achieve highly efficient rectification. We validate the idea by demonstrating significant design improvements in a <i>Cockcroft-Walton Multiplier, </i>implemented with TS based rectifiers. We emphasize the need to explore other PTMs with high endurance, thermal stability, and faster switching to enable many more innovative applications in the future.</p></div></div>

<p>Technology has become increasingly more prevalent in all aspects of society since the age of the computer. The United States Military has successfully integrated the powerful processing capabilities of computers to increase the proficiency and lethality of its Soldiers, Sailors, Marines, and Airmen. However, this increased lethality comes at risk due to the inherent vulnerabilities of computer systems to spyware, malware, and counterfeit components. Inspired by the ability of canines to seek out and find electronic devices, this research sought methods to characterize components by their “scent” using precise analytical tools. Using these tools, this thesis sought to develop and utilize non-invasive methods to show proof-of-concept for electronic device classification by volatile compounds unique to different types of components. The findings of this research proved that electronic components that vary by age, origin, type, or manufacturer emit different volatile compounds available for detection using modern two-dimensional gas chromatography and solid-phase microextraction technologies. If developed further, the methods used in this research have the potential for application in the United States Department of Defense to ensure that all electronic components installed in their systems are authentic, come from a trusted source, and can be relied upon in even the most stressful operating conditions.</p>

<p>Minimum cycle mean (MCM) is an important concept in directed graphs. From clock period optimization, timing analysis to layout optimization, minimum cycle mean algorithms have found widespread use in VLSI system design optimization. With transistor size scaling to 10nm and below, complexities and size of the systems have grown rapidly over the last decade. Scalability of the algorithms both in terms of their runtime and memory usage is therefore important. </p> <p><br></p> <p>Among the few classical MCM algorithms, the algorithm by Young, Tarjan, and Orlin (YTO), has been particularly popular. When implemented with a binary heap, the YTO algorithm has the best runtime performance although it has higher asymptotic time complexity than Karp's algorithm. However, as an efficient implementation of YTO relies on data redundancy, its memory usage is higher and could be a prohibitive factor in large size problems. On the other hand, a typical implementation of Karp's algorithm can also be memory hungry. An early termination technique from Hartmann and Orlin (HO) can be directly applied to Karp's algorithm to improve its runtime performance and memory usage. Although not as efficient as YTO in runtime, HO algorithm has much less memory usage than YTO. We propose several improvements to HO algorithm. The proposed algorithm has comparable runtime performance to YTO for circuit graphs and dense random graphs while being better than HO algorithm in memory usage. </p> <p><br></p> <p>Minimum balancing of a directed graph is an application of the minimum cycle mean algorithm. Minimum balance algorithms have been used to optimally distribute slack for mitigating process variation induced timing violation issues in clock network. In a conventional minimum balance algorithm, the principal subroutine is that of finding MCM in a graph. In particular, the minimum balance algorithm iteratively finds the minimum cycle mean and the corresponding minimum-mean cycle, and uses the mean and cycle to update the graph by changing edge weights and reducing the graph size. The iterations terminate when the updated graph is a single node. Studies have shown that the bottleneck of the iterative process is the graph update operation as previous approaches involved updating the entire graph. We propose an improvement to the minimum balance algorithm by performing fewer changes to the edge weights in each iteration, resulting in better efficiency.</p> <p><br></p> <p>We also apply the minimum cycle mean algorithm in latency insensitive system design. Timing violations can occur in high performance communication links in system-on-chips (SoCs) in the late stages of the physical design process. To address the issues, latency insensitive systems (LISs) employ pipelining in the communication channels through insertion of the relay stations. Although the functionality of a LIS is robust with respect to the communication latencies, such insertion can degrade system throughput performance. Earlier studies have shown that the proper sizing of buffer queues after relay station insertion could eliminate such performance loss. However, solving the problem of maximum performance buffer queue sizing requires use of mixed integer linear programming (MILP) of which runtime is not scalable. We formulate the problem as a parameterized graph optimization problem where for every communication channel there is a parameterized edge with buffer counts as the edge weight. We then use minimum cycle mean algorithm to determine from which edges buffers can be removed safely without creating negative cycles. This is done iteratively in the similar style as the minimum balance algorithm. Experimental results suggest that the proposed approach is scalable. Moreover, quality of the solution is observed to be as good as that of the MILP based approach.</p><p><br></p>