<p>Probabilistic computing has been proposed as an attractive alternative for bridging the computational gap between the classical computers of today and the quantum computers of tomorrow. It offers to accelerate the solution to many combinatorial optimization and machine learning problems of interest today, motivating the development of dedicated hardware. Similar to the ‘bit’ of classical computing or ‘q-bit’ of quantum computing, probabilistic bit or ‘p-bit’ serve as a fundamental building-block for probabilistic hardware. p-bits are robust classical quantities, fluctuating rapidly between its two states, envisioned as three-terminal devices with a stochastic output controlled by its input. It is possible to implement fast and efficient hardware p-bits by modifying the present day magnetic random access memory (MRAM) technology. In this dissertation, we evaluate the design and performance of low-barrier magnet (LBM) based p-bit realizations.<br> </p> <p>LBMs can be realized from perpendicular magnets designed to be close to the in-plane transition or from circular in-plane magnets. Magnetic tunnel junctions (MTJs) built using these LBMs as free layers can be integrated with standard transistors to implement the three-terminal p-bit units. A crucial parameter that determines the response of these devices is the correlation-time of magnetization. We show that for magnets with low energy barriers (Δ ≤ k_BT) the circular disk magnets with in-plane magnetic anisotropy (IMA) can lead to correlation-times in <i>sub-ns</i> timescales; two orders of magnitude smaller compared to magnets having perpendicular magnetic anisotropy (PMA). We show that this striking difference is due to a novel precession-like fluctuation mechanism that is enabled by the large demagnetization field in mono-domain circular disk magnets. Our predictions on fast fluctuations in LBM magnets have recently received experimental confirmation as well.<br></p> <p>We provide a detailed energy-delay performance evaluation of the stochastic MTJ (s-MTJ) based p-bit hardware. We analyze the hardware using benchmarked SPICE multi-physics modules and classify the necessary and sufficient conditions for designing them. We connect our device performance analysis to systems-level metrics by emphasizing problem and substrate independent figures-of-merit such as flips per second and dissipated energy per flip that can be used to classify probabilistic hardware. </p>

<p>Conventional computing is based on the concept of bits which are classical entities that are either 0 or 1 and can be represented by stable magnets. The field of quantum computing relies on qubits which are a complex linear combination of 0 and 1. Recently, the concept of probabilistic computing with probabilistic (<em>p-</em>)bits was introduced where <em>p-</em>bits are robust classical entities that fluctuate between 0 and 1. <em>P-</em>bits can be naturally represented by low-barrier nanomagnets. Probabilistic computers (<em>p-</em>computers) based on <em>p-</em>bits are domain-based hardware accelerators for Monte Carlo algorithms that can efficiently address probabilistic tasks like sampling, optimization and machine learning. </p> <p>In this dissertation, starting from the intrinsic physics of nanomagnets, we show that a compact hardware implementation of a <em>p-</em>bit based on stochastic magnetic tunnel junctions (s-MTJs) can operate at high-speeds in the order of nanoseconds, a prediction that has recently received experimental support.</p> <p>We then move to the system level and illustrate by simulation and by experiment how multiple interconnected <em>p-</em>bits can be utilized to train a Boltzmann machine built with hardware <em>p-</em>bits. We observe that even non-ideal s-MTJs can be utilized for probabilistic computing when combined with hardware-aware learning.</p> <p>Finally, we show how to build a <em>p-</em>computer to accelerate a wide variety of problems ranging from optimization and sampling to quantum computing and machine learning. The common theme for all these applications is the underlying Monte Carlo and Markov chain Monte Carlo algorithms and their parallelism enabled by a unique <em>p-</em>computer architecture.</p>