<p>Probabilistic computing has been proposed as an attractive alternative for bridging the computational gap between the classical computers of today and the quantum computers of tomorrow. It offers to accelerate the solution to many combinatorial optimization and machine learning problems of interest today, motivating the development of dedicated hardware. Similar to the ‘bit’ of classical computing or ‘q-bit’ of quantum computing, probabilistic bit or ‘p-bit’ serve as a fundamental building-block for probabilistic hardware. p-bits are robust classical quantities, fluctuating rapidly between its two states, envisioned as three-terminal devices with a stochastic output controlled by its input. It is possible to implement fast and efficient hardware p-bits by modifying the present day magnetic random access memory (MRAM) technology. In this dissertation, we evaluate the design and performance of low-barrier magnet (LBM) based p-bit realizations.<br> </p> <p>LBMs can be realized from perpendicular magnets designed to be close to the in-plane transition or from circular in-plane magnets. Magnetic tunnel junctions (MTJs) built using these LBMs as free layers can be integrated with standard transistors to implement the three-terminal p-bit units. A crucial parameter that determines the response of these devices is the correlation-time of magnetization. We show that for magnets with low energy barriers (Δ ≤ k_BT) the circular disk magnets with in-plane magnetic anisotropy (IMA) can lead to correlation-times in <i>sub-ns</i> timescales; two orders of magnitude smaller compared to magnets having perpendicular magnetic anisotropy (PMA). We show that this striking difference is due to a novel precession-like fluctuation mechanism that is enabled by the large demagnetization field in mono-domain circular disk magnets. Our predictions on fast fluctuations in LBM magnets have recently received experimental confirmation as well.<br></p> <p>We provide a detailed energy-delay performance evaluation of the stochastic MTJ (s-MTJ) based p-bit hardware. We analyze the hardware using benchmarked SPICE multi-physics modules and classify the necessary and sufficient conditions for designing them. We connect our device performance analysis to systems-level metrics by emphasizing problem and substrate independent figures-of-merit such as flips per second and dissipated energy per flip that can be used to classify probabilistic hardware. </p>

<p>Conventional computing is based on the concept of bits which are classical entities that are either 0 or 1 and can be represented by stable magnets. The field of quantum computing relies on qubits which are a complex linear combination of 0 and 1. Recently, the concept of probabilistic computing with probabilistic (<em>p-</em>)bits was introduced where <em>p-</em>bits are robust classical entities that fluctuate between 0 and 1. <em>P-</em>bits can be naturally represented by low-barrier nanomagnets. Probabilistic computers (<em>p-</em>computers) based on <em>p-</em>bits are domain-based hardware accelerators for Monte Carlo algorithms that can efficiently address probabilistic tasks like sampling, optimization and machine learning. </p> <p>In this dissertation, starting from the intrinsic physics of nanomagnets, we show that a compact hardware implementation of a <em>p-</em>bit based on stochastic magnetic tunnel junctions (s-MTJs) can operate at high-speeds in the order of nanoseconds, a prediction that has recently received experimental support.</p> <p>We then move to the system level and illustrate by simulation and by experiment how multiple interconnected <em>p-</em>bits can be utilized to train a Boltzmann machine built with hardware <em>p-</em>bits. We observe that even non-ideal s-MTJs can be utilized for probabilistic computing when combined with hardware-aware learning.</p> <p>Finally, we show how to build a <em>p-</em>computer to accelerate a wide variety of problems ranging from optimization and sampling to quantum computing and machine learning. The common theme for all these applications is the underlying Monte Carlo and Markov chain Monte Carlo algorithms and their parallelism enabled by a unique <em>p-</em>computer architecture.</p>

<p dir="ltr">Antiferromagnetic spintronics promises next-generation information processing devices with ultra-fast speeds and ultra-low power consumption. Inspired by the recent demonstration of signatures of Tunnel Magnetoresistance (TMR) in non-colinear chiral antiferromagnets of the Mn₃X family, we study the thermal stability of such magnets in both low and high barrier limits. A stochastic Landau-Lifshitz-Gilbert (s-LLG) based numerical assessment of the dynamics reveals that strong exchange fields in Mn₃Sn could lead to thermally-driven rapid fluctuations of the order parameter, viz., octupole moment. However, distinct Random Telegraph Noise (RTN)-like signals distinguish the high barrier limit from the low barrier limit - suggesting different physical phenomena in the two regimes. To that end, the correlation time for thermal fluctuations has been explored analytically following an approach inspired by Langer's theory in the high barrier limit and dephasing mechanisms in the low barrier limit. It has been shown that the dynamics in chiral antiferromagnetic nanoparticles in both regimes are an order of magnitude faster than easy plane ferromagnetic particles. The thermal instability of chiral antiferromagnets could lead to picosecond-scale random number generation in probabilistic bits -- paving the path toward ultra-fast probabilistic computation. </p>

<p dir="ltr">Probabilistic computing is a novel computing scheme that offers a more efficient approach than conventional complimentary metal-oxide-semiconductor (CMOS)-based logic in a variety of applications ranging from Bayesian inference to combinatorial optimization, and invertible Boolean logic. These applications, which have found use in the rapidly growing fields of machine learning and artificial intelligence, are traditionally computationally-intensive and so make the push for novel computing schemes that are intrinsically low-power and scalable all the more urgent.</p><p dir="ltr">The probabilistic bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires <i>tunable </i>stochasticity; low-barrier nanomagnets, in which the magnetic moment fluctuates randomly and continuously due to the presence of thermal energy, are a natural vehicle for providing the core functionality required. This dissertation describes the work done in mining the rich field of spintronics to produce devices that can act as natural hardware accelerators for probabilistic computing algorithms.</p><p dir="ltr">First, experiments exploring Fe₃O₄ nanoparticles as naturally stochastic systems are presented. Using NV center measurements on an array of such nanoparticles, it is shown that they fluctuate intrinsically at GHz frequencies at room temperature; these fluctuations could be harnessed to act as a stochastic noise source, and would, in principle, enable fast computation.</p><p dir="ltr">The focus then shifts to the development of a platform that allows for easier <i>electrical</i> readout: the low-barrier magnetic tunnel junction (MTJ). We show the work done in the development and characterization of these devices, how they respond to non-ideal environments, such as elevated temperatures and exposure to high-energy electromagnetic radiation, how their intrinsic stochasticity might be tuned with electrical currents and external magnetic fields, and then how these might be integrated with a simple transistor circuit to produce a compact low-energy implementation of a p-bit.</p><p dir="ltr">Next, by integrating our stochastic MTJs with 2D-MoS₂field-effect transistors (FETs), the first <i>on-chip </i>realization of a key p-bit building block, displaying voltage-controllable stochasticity, is demonstrated. This is followed by another key demonstration through the fabrication of stochastic MTJs directly on top of an integrated circuit platform, where the transistor circuitry is provided by 180nm-node CMOS technology.</p><p dir="ltr">In addition, supported by circuit simulations, this work provides a careful device-level analysis of the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component can influence the overall p-bit’s output. In particular, we show that – against common wisdom – a large tunnel magnetoresistance (TMR) is not the best choice for p-bits; bimodal telegraphic fluctuations are highly undesirable and are a sign of a slow device; and an ideal inverter with a large gain is unsuitable for p-bit applications due to the higher likelihood of unwanted plateaus in the resulting p-bit’s output.</p><p dir="ltr">This analysis is extended to consider the impact of such non-ideal p-bits when used to construct probabilistic circuits, with the focus on the emulation of the Boolean logic AND gate through a three p-bit correlated system. It is found that a probabilistic circuit made with ideal p-bits can accurately emulate the function of an AND gate, while the non-ideal p-circuits suffer from an increased error rate in emulating the AND gate’s truth table.</p><p dir="ltr">The understanding gained at the individual device level, in what makes a good or bad MTJ, to how the different components of the 3T-1MTJ p-bit can affect its output, and subsequently how non-ideal p-bits can impact circuit performance, can be important for the future realization of scaled on-chip p-bit networks.</p>