While probabilistic neural networks are a staple of the neural network field, their study in the context of real hardware has been limited. Probabilistic spin logic entails the study of probabilistic neurons that have real hardware counterparts. This comes under a new effort, termed Purdue-P, whose goal it is to develop efficient, probabilistic neural network hardware to solve some of today’s most difficult problems. An important step in this effort has been the development of a website, purdue.edu/p-bit, to act as a “front page” for the effort. This website introduces the idea of probabilistic spin logic to newcomers, houses an online web simulator and blog, and provides instructions on how to access a powerful asynchronous p-computing co-processor through the cloud. The thoughts behind the flow of content, the web simulator, and cloud access of the co-processor constitute the crux of the thesis.

<p>The recent groundbreaking demonstrations of quantum supremacy in noisy intermediate scale quantum (NISQ) computing era has triggered an intense activity in establishing finer boundaries between classical and quantum computing. In this dissertation, we use established techniques based on quantum Monte Carlo (QMC) to map quantum problems into probabilistic networks where the fundamental unit of computation, p-bit, is inherently probabilistic and can be tuned to fluctuate between ‘0’ and ‘1’ with desired probability. We can view this mapped network as a Boltzmann machine whose states each represent a Feynman path leading from an initial configuration of q-bits to a final configuration. Each such path, in general, has a complex amplitude, ψ which can be associated with a complex energy. The real part of this energy can be used to generate samples of Feynman paths in the usual way, while the imaginary part is accounted for by treating the samples as complex entities, unlike ordinary Boltzmann machines where samples are positive. This mapping of a quantum circuit onto a Boltzmann machine with complex energies should be particularly useful in view of the advent of special-purpose hardware accelerators known as Ising Machines which can obtain a very large number of samples per second through massively parallel operation. We also demonstrate this acceleration using a recently used quantum problem and speeding its QMC simulation by a factor of ∼ 1000× compared to a highly optimized CPU program. Although this speed-up has been demonstrated using a graph colored architecture in FPGA, we project another ∼ 100× improvement with an architecture that utilizes clockless analog circuits. We believe that this will contribute significantly to the growing efforts to push the boundaries of the simulability of quantum circuits with classical/probabilistic resources and comparing them with NISQ-era quantum computers. </p>