This graduation thesis deals with a software design of burglar alarm. The software has been developed in compliance with the applicable standards and regulations governing burglar alarm designs and on the basis of practical experience with designing and implementing electronic security systems. The software is written in C# and uses .NET platform. On the ground of that, this software can be run on any computer with the Windows operation system. Any ground plan picture file can be used as the underlying project map on which all the object security system can be built. It makes it possible to produce both wire and wireless electronic security systems. The software includes an editable database of components and conductors used in the electronic security alarms. The database components can be created, edited and deleted through the software. The database has been saved in format XML. The software also includes a folder of picture files containing photographs of the components and schematic symbols used in the software. You use a mouse to drag and drop individual components into the ground plan picture, where they are well arranged in a tree structure. The components can be interconnected by a conductor, which enables creation of a precise design of the electronic security system of the object. The software output includes drawings, bills of material and pricing. As for the space components, you can graphically display their range and thus visually confirm the design. The software includes automatic design verification. There, you can verify whether the right components have been used and whether the designed conductor lengths are acceptable, whether they correspond with the system load, and whether the voltage drops on the conductors do not exceed the permitted limit. The software has been developed for all electronic security system designers and for engineers attending to these problems.

<p dir="ltr">Semiconductor technology has propelled human society into the information age, and that progress continues. Silicon CMOS device has been aggressively scaled down to 5 nm technology node. To further boost the on-state performance, MOS technology based on high-mobility channels such as III-V and Ge have been intensively studied. 3D structures such as FinFETs and gate-all-around (GAA) FETs are also applied to III-V and Ge to improve the electrostatic control of the channels for the ultimate scaling. </p><p><br></p><p dir="ltr">Traditional semiconductor device characterization techniques are inapplicable to devices created through these novel materials and device structures. This work applies various techniques to characterize a wide variety of semiconductor devices, in addition to presenting novel techniques studying the reliability of commercial off the shelf (COTS) products. Finally, the design of an ultra-low-power RF ASIC implementing wireless neural recording and stimulation, designed for cranial implantation, will be presented.</p>