In recent years, research in the field of automation has been advancing quickly in the direction of wireless networks of sensors and actuators. This development has introduced a need to reduce the amount of communication. A number of different alternative schemes have been proposed. They are usually divided into event-triggered schemes and self-triggered ones. The main purpose of this Master's thesis was to further develop and evaluate the sesampling schemes, focusing on their needed communication. The effect on control performance by the different schemes was also taken into account. Because of the difficulty in performing a theoretical comparison, the thesis focused on evaluating the schemes in simulations and in experiments on real industrial processes. The results indicate that simply using a slower periodic scheme may reduce as much communication without losing much performance as the more flexible schemes. This would imply that investing further into the other schemes may be of waste. However, using an event-triggered scheme with improvements introduced in this report may offer some advantages when it comes to performance and simplicity in setup. Maybe more importantly, it is safer during rapidly changing conditions, which also makes it very unlikely that a slow periodic sampler would ever be implemented on a real system. The results in general are very positive with communication reductions of over 90% when using a well tuned base sampling interval and over 99% when the comparison is made to current implementations in the industry, all without significant loss of performance.

<p>This master thesis describes a design exploration of a circuit capable of measuring high speed signals without adding significant capacitive load to the measuring node. </p><p>It is designed in a 0.13 CMOS process with a supply voltage of 1.2 Volt. The circuit is a master and slave, track-and-hold architecture incorporated with a capacitive voltage divider and a NMOS source follower as input buffer to protect the measuring node and increase the input voltage range. </p><p>This thesis presents the implementation process and the theory needed to understand the design decisions and consideration throughout the design. The results are based on transistor level simulations performed in Cadence Spectre. </p><p>The results show that it is possible to observe the analog behaviour of a high speed signal by down converting it to a lower frequency that can be brought off-chip. The trade off between capacitive load added to the measuring node and input bandwidth of the measurment circuit is also presented.</p>

This master thesis describes a design exploration of a circuit capable of measuring high speed signals without adding significant capacitive load to the measuring node. It is designed in a 0.13 CMOS process with a supply voltage of 1.2 Volt. The circuit is a master and slave, track-and-hold architecture incorporated with a capacitive voltage divider and a NMOS source follower as input buffer to protect the measuring node and increase the input voltage range. This thesis presents the implementation process and the theory needed to understand the design decisions and consideration throughout the design. The results are based on transistor level simulations performed in Cadence Spectre. The results show that it is possible to observe the analog behaviour of a high speed signal by down converting it to a lower frequency that can be brought off-chip. The trade off between capacitive load added to the measuring node and input bandwidth of the measurment circuit is also presented.