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Gate level coverage of a behavioral test generator

Use of traditional gate level test generation techniques is prohibitively expensive and time consuming for VLSI chips. High level approaches to test generation have been proposed to improve the efficiency of test generation, e.g., the Behavioral Test Generator developed at Virginia Tech generates test vectors from high level Behavioral VHDL descriptions. To validate the utility of these test vectors, it needs to be established that they provide adequate coverage at the gate level. This thesis shows that test vectors obtained from the Behavioral Test Generator provide adequate coverage for the equivalent gate level circuit. A system that was developed to effectively evaluate the test vectors is presented. The implementation of Heuristic Test Generator to improve the coverage of the Behavioral Test Generator is explained. / Master of Science

Identiferoai:union.ndltd.org:VTETD/oai:vtechworks.lib.vt.edu:10919/45598
Date10 November 2009
CreatorsBaweja, Gunjeetsingh
ContributorsElectrical Engineering, Armstrong, James R., Cyre, Walling R., Gray, Festus Gail
PublisherVirginia Tech
Source SetsVirginia Tech Theses and Dissertation
LanguageEnglish
Detected LanguageEnglish
TypeThesis, Text
Formatx, 158 leaves, BTD, application/pdf, application/pdf
RightsIn Copyright, http://rightsstatements.org/vocab/InC/1.0/
RelationOCLC# 28513985, LD5655.V855_1993.B394.pdf

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