The design of SoC is growing into more complicated, hence it is necessary to determine an efficient way to develop an SoC. If we can explore the relation between hardware architecture and software operation, there will be a great help for designing SoC platform. This paper builds the highly abstract simulation platform by using the development tool of SystemC and Coware for 3D graphics SoC. SystemC is entirely based on C++, so that Coware Inc. supports many TLM IP modules (like ARM CPU, ARM BUS, Memory, and etc.) for designer. For the purpose of fast building and modifying module by designer, this paper discusses 1. the behavior module performance in 3D Graphics Traditional Architecture, Tile-based Architecture of non-pipeline, pipeline, and GE&DMA Concurrence. 2. If it can use the software application to control procedure order of GE and RE, it would decrease the read/write times for RE reading from Tile. 3. To modify the read/write mechanism of Tile Buffer and change the returned values from memory, it would reduce the read/write times from memory. 4. And we need to observe FIFO sizes of traditional architecture to estimate affection performance.5. It uses Tile-Divider to predict the cutting triangle. Finally, 6. it modifies the AHB bus to AXI bus and divides single memory; therefore it can reduce the waiting bus time of GE and RE and improve the efficient of bus communication.
| Identifer | oai:union.ndltd.org:NSYSU/oai:NSYSU:etd-0907109-153522 |
| Date | 07 September 2009 |
| Creators | Lin, Ching-Yuan |
| Contributors | Shen-Fu Hsiao, Ing-Jer Huang, Chung-nan Lee, Shiann-Rong Kuang |
| Publisher | NSYSU |
| Source Sets | NSYSU Electronic Thesis and Dissertation Archive |
| Language | Cholon |
| Detected Language | English |
| Type | text |
| Format | application/pdf |
| Source | http://etd.lib.nsysu.edu.tw/ETD-db/ETD-search/view_etd?URN=etd-0907109-153522 |
| Rights | off_campus_withheld, Copyright information available at source archive |
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