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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.

3D Graphics Application System

Werczak, Slawomir 12 1900 (has links)
This project is about a 3D graphics system for engineers and architects. Its goal is twofold: to provide tools for drawing 3D models, and to create a database support system where data related to these models would be stored (at present the first part has been implemented). Costs, materials, calculations of loads, stresses, and other important factors will be available to the user during the whole design process. The system will therefore allow for drawing realistic projects, not just conceptual visual models. The drawing tools provided by the system include a few drawing techniques and viewing functions. The system’s drawing routines operate on sets of points, lines, or components so that they are very fast and efficient. This approach to the method of drawing along with the description of the system are given in the following write-up. / Thesis / Master of Science (MS)

Memory Allocation of 3D Graphics Data for a 3D Hardware Accelerator

Chen, Hung-Yu 15 August 2008 (has links)
Hardware implementation is one of common solutions for accelerating 3D Graphics Pipelining Application. In this thesis, our purpose is to probe into the effect of 3D graphics system performance, according to the memory allocation of 3D graphics data and bus architecture for 3D graphics system-on-chip. And we also improve performance of whole application system efficiently by existent hardware resource. For getting the purpose, we use system level of simulation to observe and analyze the access of hardware accelerator in system and find out the key for improving performance. In this paper, we use ESL design to aid us for system simulation. Besides simulation time is much faster than RTL, abstract description is easy to implement and analyze. In memory organization, we must understand the relation of access data of 3D hardware with SDRAM, and reallocation memory. So, we divide each data and put them in different banks of SDRAM, scratch memory of system and built-in memory of hardware. Besides we increase the bandwidth of system bus by using multilayer architecture in system bus, we modify software to up the access times for improving performance. The experiment results point out that we speed up performance for 1.62 times.

Shadow computation for 3D interaction and animation

Chrysanthou, Yiorgos January 1996 (has links)
No description available.

Exploring the Brain : Interactivity and Learning

Oscarsson, Jacob January 2016 (has links)
This study has examined whether the use of an interactive 3D model of the human brain would be a more effective way of teaching it's anatomy in comparison to traditional book and paper-based techniques. The artefact created for the project was a three dimensional model of the brain made up of several anatomical structures that could be dissected to provide the user with a more accurate sense of the spatial relationships between each structure.  The study conducted did not give sufficient information to accurately answer the research question, but interviews conducted during the experiment show interest in the technology. If developed, there could be potential for the use of this type of technology in the future.

SoC Integration and Verification of a 3D Graphics SoC

Huang, Tzu-Ming 26 July 2011 (has links)
While consumer demand for electronic equipment and more mature systems integration capabilities, it makes the system complexity of chip design increasing significantly. Also accompany an issue is how to efficiently and accurately verify that such a large-scale chip. In this thesis, we make 3D graphics SoC as a case study, investigate the various aspect, i.e. architecture design, system integration, verification methods and verification platform. This thesis proposes a verification methodology with unified test pattern from system modeling level to test chip level, and via increase of the abstraction level of test patterns, that avoided the way through the manual to generate the test patterns. Not only eliminate manual editing effort and reduce the possibility of error, but also allows developers to more focus on algorithm design and functional verification. In addition, through the pre-described of test scenario (Test-bench) which automated verification and comparison methodology. The efficiency of regression test will be increased. And it's much easier to meet the constraint of time to market. However, In order to demonstrate our chip on new prototyping based board. We not only modified the channel of 3DG chip, but also develop a high-performance bus bridge to keep the efficient of exchange data between two system buses which in platform board and our SoC. And shorten the longest path of the overall system so that system clock rate could be enhanced from 82.6MHz to 120.4 MHz system clock rate.

A Unified System/RTL/FPGA/Chip Verification Methodology for a 3D Graphics SoC

Huang, Wei-Sheng 15 August 2008 (has links)
In recent years, a theme for generally discussion in IC design domain is how to do the efficient verification in complex SoC environment and raise the confidence when chip taped-out. But when we face the different abstraction levels of verification environment like the System Modeling Level, Register Transfer Level, FPGA Emulation Level and Chip Level verification environment, how to unifiy test-patterns and makes them can be reused and do mutual-verification in different abstraction level verification environments is our main topic. Therefore, this thesis proposed a verification methodology that based on the 3D graphics SoC and unified the test patterns that let the different abstraction levels of verification environment can use the same test patterns. And to face the exetensive test patterns of 3DG SoC, we also proposed an automatic verification mechanism which can run the simulation and compare the simulation results automatically and improve the verification efficiency. Finally, we also share the 3DG SoC integration and verification experience from front-end to back-end, hope to makes everyone understand the related flow from RTL design to test-chip testing.

Performance Modeling for a 3D Graphics SoC

Lin, Ching-Yuan 07 September 2009 (has links)
The design of SoC is growing into more complicated, hence it is necessary to determine an efficient way to develop an SoC. If we can explore the relation between hardware architecture and software operation, there will be a great help for designing SoC platform. This paper builds the highly abstract simulation platform by using the development tool of SystemC and Coware for 3D graphics SoC. SystemC is entirely based on C++, so that Coware Inc. supports many TLM IP modules (like ARM CPU, ARM BUS, Memory, and etc.) for designer. For the purpose of fast building and modifying module by designer, this paper discusses 1. the behavior module performance in 3D Graphics Traditional Architecture, Tile-based Architecture of non-pipeline, pipeline, and GE&DMA Concurrence. 2. If it can use the software application to control procedure order of GE and RE, it would decrease the read/write times for RE reading from Tile. 3. To modify the read/write mechanism of Tile Buffer and change the returned values from memory, it would reduce the read/write times from memory. 4. And we need to observe FIFO sizes of traditional architecture to estimate affection performance.5. It uses Tile-Divider to predict the cutting triangle. Finally, 6. it modifies the AHB bus to AXI bus and divides single memory; therefore it can reduce the waiting bus time of GE and RE and improve the efficient of bus communication.

A Software Tool Suite for Performance Monitoring and Verification of a 3D Graphics SoC

Ho, Tsung-Yu 09 September 2009 (has links)
System-on-a-Chip (SoC) has been applied in numerous varieties of consumer electronics, especially in mobile device. The user interface of mobile device changes from traditional 2D graphic interface into the complicated 3D graphic interface. The fully computation of 3D graphics on SoC aims for low power dissipation that must be the key factor of SoC development. This thesis proposes a software tool suite for performance monitoring and verification. The performance monitoring contains real-time monitoring, static counter analysis, and hardware sub-module record. And the verification tool includes scenes capturing, scenes comparison, and error ratio analysis. After proposing the software tool suite, we can do: (1) find out the errors between hardware and software; (2) analyze the accuracy of hardware computation; (3) Real-time monitoring hardware vertex, pixel, and memory read/write counts.

Modélisation et animation interactive de visages virtuels de dessins animés

Monjaux, Perrine 10 December 2007 (has links) (PDF)
La production de dessins animés 2D qui suit actuellement un schéma mis en place dans les années 1920 fait intervenir un très grand nombre de compétences humaines et de métiers différents. Par opposition à ce mode de travail traditionnel, la production de films de synthèse 3D, en exploitant les technologies et les outils les plus récents de modélisation et d'animation 3D, s'affranchit en bonne partie de cette composante artisanale et vient concurrencer l'industrie du dessin animé traditionnel en termes de temps et coûts de fabrication. <br />Les défis à relever par l'industrie du dessin animé 2D se posent donc en termes de :<br />1. Réutilisation des contenus selon le paradigme d'accès «Create once, render many»,<br />2. Facilité d'échange et de transmission des contenus ce qui nécessite de disposer d'un unique format de représentation,<br />3. Production efficace et économique des contenus requérant alors une animation automatisée par ordinateur.<br />Dans ce contexte compétitif, cette thèse, réalisée dans le cadre du projet industriel TOON financé par la société Quadraxis (www.quadraxis.com) et supporté par l'Agence Nationale de Valorisation de la Recherche (ANVAR), a pour objectif de contribuer au développement d'une plate-forme de reconstruction, déformation et animation de modèles 3D de visages pour les dessins animés 2D. Vecteurs de la parole et des expressions, les visages nécessitent en effet une attention particulière quant à leur modélisation et animation conforme aux souhaits des créateurs de dessins animés. <br />Un état de l'art des méthodes, outils et systèmes contribuant à la création de modèles 3D faciaux et à leur animation est présenté et discuté au regard des contraintes spécifiques qui régissent les règles de création des dessins animés 2D et la chaîne de fabrication traditionnelle.<br />Ayant identifié les verrous technologiques à lever, nos contributions ont porté sur :<br /> l'élaboration d'une méthode de conception de visages virtuels 3D à partir d'une part d'un modèle 3D de type seamless, adapté aux exigences d'animation sans rupture, et d'autre part d'un ensemble de dessins 2D représentant les caractéristiques faciales,<br /> la mise au point d'une procédure de création de poses clés, mettant en œuvre plusieurs méthodes de déformation non-rigide,<br /> la conception d'un module d'animation 3D compatible avec le standard MPEG-4/AFX. <br /><br />Les développements réalisés, intégrés dans un premier prototype de la plate-forme FaceTOON, montrent un gain en temps de 20% sur l'ensemble de la chaîne de production tout en assurant une complète interopérabilité des applications via le standard MPEG-4.

Implementation of Arithmetic Component Generator in 3D Graphics Geometry System

Wei, Ping-chung 20 August 2007 (has links)
We develop a datapath generator for various arithmetic function units required in the design of the geometry subsystem in the 3D graphics application. The operations considered in the geometry subsystem include coordinate transformations and lighting. The generator will automatically generate efficient designs of function units based on the requirements of area, speed and accuracy. The major function units designed in this thesis are divided into two parts: multiplier-related function units and single-value arithmetic function units. In the generation of multipliers, we consider the design of truncated multipliers to reduce the area cost. In the design of other function evaluators, we consider two table-based methods: piecewise interpolation table-based method and the multipartite table-based method.

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