In recent years, a theme for generally discussion in IC design domain is how to do the efficient verification in complex SoC environment and raise the confidence when chip taped-out. But when we face the different abstraction levels of verification environment like the System Modeling Level, Register Transfer Level, FPGA Emulation Level and Chip Level verification environment, how to unifiy test-patterns and makes them can be reused and do mutual-verification in different abstraction level verification environments is our main topic. Therefore, this thesis proposed a verification methodology that based on the 3D graphics SoC and unified the test patterns that let the different abstraction levels of verification environment can use the same test patterns. And to face the exetensive test patterns of 3DG SoC, we also proposed an automatic verification mechanism which can run the simulation and compare the simulation results automatically and improve the verification efficiency. Finally, we also share the 3DG SoC integration and verification experience from front-end to back-end, hope to makes everyone understand the related flow from RTL design to test-chip testing.

Submitted by Johnny Rodrigues (johnnyrodrigues@ufcg.edu.br) on 2018-08-27T17:42:49Z No. of bitstreams: 1 HELDER FERNANDO DE ARAUJO OLIVEIRA - DISSERTAÇÃO PPGCC 2010..pdf: 2110687 bytes, checksum: 5d2a2c0f6c5039c3f21dd8219d20f122 (MD5) / Made available in DSpace on 2018-08-27T17:42:49Z (GMT). No. of bitstreams: 1 HELDER FERNANDO DE ARAUJO OLIVEIRA - DISSERTAÇÃO PPGCC 2010..pdf: 2110687 bytes, checksum: 5d2a2c0f6c5039c3f21dd8219d20f122 (MD5) Previous issue date: 2010-06-16 / O processo de desenvolvimento de um circuito digital complexo pode ser composto por diversas etapas. Uma delas é a verificação funcional. Esta etapa pode ser considerada uma das mais importantes, pois tem como objetivo demonstrar que as funcionalidades do circuito a ser produzido estão em conformidade com a sua especificação. Porém, além de ser uma fase com grande consumo de recursos, a complexidade da verificação funcional cresce diante da complexidade do hardware a ser verificado. Desta forma, o uso de uma metodologia de verificação funcional eficiente e de ferramentas que auxiliem o engenheiro de verificação funcional são de grande valia. Neste contexto, este trabalho realiza uma reformulação da metodologia de verificação funcional VeriSC, originando uma nova metodologia, denominada BVM (Brazil-IP Verification Methodology). VeriSC é implementada em SystemC e utiliza as bibliotecas SCV (SystemC Verification Library) e BVE (Brazil-IP Verification Extensions), enquanto BVM é implementada em SystemVerilog e baseada em conceitos e biblioteca de OVM (Open Verification Methodology). Além disto, este trabalho visa a adequação da ferramenta de apoio à verificação funcional eTBc (Easy Testbench Creator) para suportar BVM. A partir do trabalho realizado, é possível constatar, mediante estudos de caso no âmbito do projeto Brazil-IP, que BVM traz um aumento da produtividade do engenheiro de verificação na realização da verificação funcional, em comparação à VeriSC / The development process of a complex digital circuit can consist of several stages. One of them is the functional verification. This stage can be considered one of the most important because it aims to demonstrate that a circuit functionality to be produced is in accordance with its specification. However, besides being a stage with large consumption of resources, the complexity of functional verification grows according to the complexity of the hardware to be verified. Thus, the use of an effective functional verification methodology and tools to help engineer the functional verification are of great value. Within this context, this work proposes a reformulation of the functional verification methodology VeriSC, resulting in a new methodology called BVM (Brazil-IP Verification Methodology). VeriSC is implemented in SystemC and uses the SCV (SystemC Verification Library) and BVE (Brazil-IP Verification Extensions) libraries, while BVM is implemented and based on SystemVerilog and OVM (Open Verification Methodology) concepts and library. Furthermore, this study aims the adequacy of the functional verification tool eTBc (testbench Easy Creator), to support BVM. From this work it can be seen, based on case studies under the Brazil-IP project, that BVM increase the productivity of the engineer in the functional verification stage when compared to VeriSC.

Este trabalho propõe o desenvolvimento de uma metodologia para a verificação circuitos integrados de sinais mistos de uso em sistemas de comunicação que operem em modo simplex. Deseja-se aproveitar as características inversas de recepção e transmissão para otimizar o processo de verificação. Para o desenvolvimento desta metodologia de verificação, teve-se como objetivo estudar metodologias de verificação de circuitos integrados de sinais mistos existentes e sua evolução, as quais têm garantido cada vez mais a funcionalidade de circuitos integrados que são compostos por blocos analógicos e digitais. A metodologia é aplicada a um dos circuitos que compõem um sistema otimizado de transmissão de dados via satélite (Transponder para Satélite). O sistema de transmissão de dados via satélite, foco do trabalho, é composto por receptores, transmissores e conversores analógico digital e um Processador Digital de Sinais - Digital Signal Processing (DSP), todos desenvolvidos em hardware. A metodologia de verificação compreende no desenvolvimento de uma estrutura de verificação capaz de estimular os blocos digitais e analógicos com o objetivo de garantir a funcionalidade de cada um dos componentes do IP Transponder. Em uma etapa seguinte, foi possível estimular o IP Transponder de forma integrada, no que se refere aos os blocos digitais e analógicos, assim como os de transmissão e recepção. Ressalta-se ainda que todo o desenvolvimento foi realizado em alto nível, ou seja, todas as características e propriedades foram observadas utilizando-se somente simuladores para garantir a funcionalidade do circuito integrado de sinais mistos que compõe o IP Transponder para satélite. / This work proposes the development of a verification methodology, used during the verification process of a mixed signal integrated circuit, which represents a communication system operating in simplex mode. In order to optimize the verification process, reverse reception and transmission will be used. With the intention of developing our verification methodology, a study on other methodologies used for the verification of mixed signals integrated circuits and the evolution of such methodologies was carried out. The proposed methodology has been applied in an advanced circuit used to establish data transmission by satellite (Transponder for Satellite). The targeted data transmission system is composed by analog receptor and transmitter, analog to digital converters and a digital signal-processing unit, all developed in hardware. The verification methodology consists of two steps: first, the development of a verification structure that are able to stimulate digital and analog blocks in order to guarantee the functionality of each system component. In a following step, the developed verification environment provides the stimulation for all the Transponder IP (digital and analog blocks), and for transmission and reception blocks as well. The verification process development was performed in high level, meaning all the characteristics and properties has been observed using only simulators with the purpose of guarantee the functionality of the mixed signal integrated circuit that composes the satellite Transponder IP.

Este trabalho propõe o desenvolvimento de uma metodologia para a verificação circuitos integrados de sinais mistos de uso em sistemas de comunicação que operem em modo simplex. Deseja-se aproveitar as características inversas de recepção e transmissão para otimizar o processo de verificação. Para o desenvolvimento desta metodologia de verificação, teve-se como objetivo estudar metodologias de verificação de circuitos integrados de sinais mistos existentes e sua evolução, as quais têm garantido cada vez mais a funcionalidade de circuitos integrados que são compostos por blocos analógicos e digitais. A metodologia é aplicada a um dos circuitos que compõem um sistema otimizado de transmissão de dados via satélite (Transponder para Satélite). O sistema de transmissão de dados via satélite, foco do trabalho, é composto por receptores, transmissores e conversores analógico digital e um Processador Digital de Sinais - Digital Signal Processing (DSP), todos desenvolvidos em hardware. A metodologia de verificação compreende no desenvolvimento de uma estrutura de verificação capaz de estimular os blocos digitais e analógicos com o objetivo de garantir a funcionalidade de cada um dos componentes do IP Transponder. Em uma etapa seguinte, foi possível estimular o IP Transponder de forma integrada, no que se refere aos os blocos digitais e analógicos, assim como os de transmissão e recepção. Ressalta-se ainda que todo o desenvolvimento foi realizado em alto nível, ou seja, todas as características e propriedades foram observadas utilizando-se somente simuladores para garantir a funcionalidade do circuito integrado de sinais mistos que compõe o IP Transponder para satélite. / This work proposes the development of a verification methodology, used during the verification process of a mixed signal integrated circuit, which represents a communication system operating in simplex mode. In order to optimize the verification process, reverse reception and transmission will be used. With the intention of developing our verification methodology, a study on other methodologies used for the verification of mixed signals integrated circuits and the evolution of such methodologies was carried out. The proposed methodology has been applied in an advanced circuit used to establish data transmission by satellite (Transponder for Satellite). The targeted data transmission system is composed by analog receptor and transmitter, analog to digital converters and a digital signal-processing unit, all developed in hardware. The verification methodology consists of two steps: first, the development of a verification structure that are able to stimulate digital and analog blocks in order to guarantee the functionality of each system component. In a following step, the developed verification environment provides the stimulation for all the Transponder IP (digital and analog blocks), and for transmission and reception blocks as well. The verification process development was performed in high level, meaning all the characteristics and properties has been observed using only simulators with the purpose of guarantee the functionality of the mixed signal integrated circuit that composes the satellite Transponder IP.

This study is focused on web services testing with SoapUI tool, particularly on verification methodology for Web services testing with SoapUI. The main objective of this thesis is to verify the methodology. Specific goals include introduction to basic concepts and principles related to web services, a description of the testing process including types of the tests and specifics of testing web services, introduction of methodology for Web services testing with SoapUI, practical verification of the methodology on the real information system and a suggestion of how to adapt the methodology on the basis of the verification. The theoretical part summarizes basic knowledge of the web services technology and web services testing. Especially it is devoted to description of the methodology for Web services testing with SoapUI and to the introduction of the SoapUI tool. The practical part consists of the introduction of the test system in Česká pojišťovna, a. s. and Generali pojišťovna, a. s., where the methodology is verified. Next the methodology for Web services testing with SoapUI is verified. Based on this verification, there are suggestions of how to adapt or extend the methodology.

Submitted by Johnny Rodrigues (johnnyrodrigues@ufcg.edu.br) on 2018-08-15T15:44:40Z No. of bitstreams: 1 ANA KARINA DE OLIVEIRA ROCHA - DISSERTAÇÃO PPGCC 2008..pdf: 1111308 bytes, checksum: d22b0170a207a14988449565a953bfb2 (MD5) / Made available in DSpace on 2018-08-15T15:44:40Z (GMT). No. of bitstreams: 1 ANA KARINA DE OLIVEIRA ROCHA - DISSERTAÇÃO PPGCC 2008..pdf: 1111308 bytes, checksum: d22b0170a207a14988449565a953bfb2 (MD5) Previous issue date: 2008-05-16 / A necessidade de sistemas cada vez mais complexos é uma realidade em quase todas as áreas de aplicação da eletrônica. Os avanços recentes da microeletrônica possibilitam o surgimento de soluções inovadoras para diversos problemas do mundo moderno, devido à criação, em ritmo cada vez mais acelerado, de sistemas digitais de qualidade, sendo possível integrar dezenas de milhões de transistores em um único chip, com baixo custo operacional. Esses sistemas estão em constante evolução, impulsionada pelo desenvolvimento da indústria de semicondutores. Assim, há fortes pressões de mercado para a disponibilização de novos produtos com um número cada vez maior de funcionalidades. As implementações dos circuitos eletrônicos complexos necessitam da utilização de metodologias eficientes e automatizadas, que auxiliem na diminuição das falhas de projeto, a exemplo da metodologia de verificação funcional denominada VeriSC, que fornece testbenches e utiliza a biblioteca SCV (SystemC Verification Library), mas se restringe à verificação de circuitos digitais que processam transações temporais síncronas. O trabalho desenvolvido consiste na criação de um mecanismo de implementação de transações temporais, aplicada à metodologia de verificação funcional VeriSC, tornando-a uma metodologia de verificação eficiente também para circuitos digitais capazes de processar transações temporais assíncronas. / The necessity for more complex systems is a reality in almost all electronic application areas. Recent advances in microelectronics make possible the appearance of innovative solutions for several problems of the modern world, due to the creation in accelerated rhythm of quality digital systems, allowing the integration of tens of millions of transistors in a single chip with low operational cost. Those systems are in constant evolution promoted by the development of the semiconductors industry. Thus, there are strong pressures from the market to make new products available with an increasing number of functionalities. Implementations of complex electronic circuits must use of efficient and automated verification methodologies, which help in reducing design failures. In this context VeriSC, a functional verification methodology which provides testbenches and uses the SCV Library (SystemC Verification Library), but it is restricted to the digital circuit verification that has only synchronous time transactions. This work consists in creating a mechanism for the implementation of time transactions, applied to the VeriSC functional verification methodology, and in making it an efficient methodology for digital circuits capable of processing asynchronous time transactions.

The RISC-V platform is one of the leaders in the computer and embedded systems industry. With the increasing use of these systems, the demand for available peripherals for the implementations of this platform is growing. This thesis deals with the FU540-C000 processor from SiFive company, which is one of the implementations of the RISC-V architecture, and its basic peripherals. Based on the analysis, an UART circuit for asynchronous serial communication was selected from the peripherals of this processor. The aim of this master thesis is to design and implement the peripheral in one of the languages for the description of digital circuits, and then create a verification environment, through which the functionality of the implementation will be verified.

Při vývoji současných číslicových systémů, např. vestavěných systému a počítačového hardware, je nutné hledat postupy, jak zvýšit jejich spolehlivost. Jednou z možností je zvyšování efektivity a rychlosti verifikačních procesů, které se provádějí v raných fázích návrhu. V této dizertační práci se pozornost věnuje verifikačnímu přístupu s názvem funkční verifikace. Je identifikováno několik výzev a problému týkajících se efektivity a rychlosti funkční verifikace a ty jsou následně řešeny v cílech dizertační práce. První cíl se zaměřuje na redukci simulačního času v průběhu verifikace komplexních systémů. Důvodem je, že simulace inherentně paralelního hardwarového systému trvá velmi dlouho v porovnání s během v skutečném hardware. Je proto navrhnuta optimalizační technika, která umisťuje verifikovaný systém do FPGA akcelerátoru, zatím co část verifikačního prostředí stále běží v simulaci. Tímto přemístěním je možné výrazně zredukovat simulační režii. Druhý cíl se zabývá ručně připravovanými verifikačními prostředími, která představují výrazné omezení ve verifikační produktivitě. Tato režie však není nutná, protože většina verifikačních prostředí má velice podobnou strukturu, jelikož využívají komponenty standardních verifikačních metodik. Tyto komponenty se jen upravují s ohledem na verifikovaný systém. Proto druhá optimalizační technika analyzuje popis systému na vyšší úrovni abstrakce a automatizuje tvorbu verifikačních prostředí tím, že je automaticky generuje z tohoto vysoko-úrovňového popisu. Třetí cíl zkoumá, jak je možné docílit úplnost verifikace pomocí inteligentní automatizace. Úplnost verifikace se typicky měří pomocí různých metrik pokrytí a verifikace je ukončena, když je dosažena právě vysoká úroveň pokrytí. Proto je navržena třetí optimalizační technika, která řídí generování vstupů pro verifikovaný systém tak, aby tyto vstupy aktivovali současně co nejvíc bodů pokrytí a aby byla rychlost konvergence k maximálnímu pokrytí co nejvyšší. Jako hlavní optimalizační prostředek se používá genetický algoritmus, který je přizpůsoben pro funkční verifikaci a jeho parametry jsou vyladěny pro tuto doménu. Běží na pozadí verifikačního procesu, analyzuje dosažené pokrytí a na základě toho dynamicky upravuje omezující podmínky pro generátor vstupů. Tyto podmínky jsou reprezentovány pravděpodobnostmi, které určují výběr vhodných hodnot ze vstupní domény. Čtvrtý cíl diskutuje, zda je možné znovu použít vstupy z funkční verifikace pro účely regresního testování a optimalizovat je tak, aby byla rychlost testování co nejvyšší. Ve funkční verifikaci je totiž běžné, že vstupy jsou značně redundantní, jelikož jsou produkovány generátorem. Pro regresní testy ale tato redundance není potřebná a proto může být eliminována. Zároveň je ale nutné dbát na to, aby úroveň pokrytí dosáhnutá optimalizovanou sadou byla stejná, jako u té původní. Čtvrtá optimalizační technika toto reflektuje a opět používá genetický algoritmus jako optimalizační prostředek. Tentokrát ale není integrován do procesu verifikace, ale je použit až po její ukončení. Velmi rychle odstraňuje redundanci z původní sady vstupů a výsledná doba simulace je tak značně optimalizována.

With industry expectations of billions of Internet-connected things, commonly referred to as the IoT, we see a growing demand for high-performance on-chip bus architectures with the following attributes: small scale, low energy, high security, and highly configurable structures for integration, verification, and performance estimation. Our research thus mainly focuses on addressing these key problems and finding the balance among all these requirements that often work against each other. First of all, we proposed a low-cost and low-power System-on-Chips (SoCs) architecture (IBUS) that can frame data transfers differently. The IBUS protocol provides two novel transfer modes – the block and state modes, and is also backward compatible with the conventional linear mode. In order to evaluate the bus performance automatically and accurately, we also proposed an evaluation methodology based on the standard circuit design flow. Experimental results show that the IBUS based design uses the least hardware resource and reduces energy consumption to a half of an AMBA Advanced High-Performance Bus (AHB) and Advanced eXensible Interface (AXI). Additionally, the valid bandwidth of the IBUS based design is 2.3 and 1.6 times, respectively, compared with the AHB and AXI based implementations. As IoT advances, privacy and security issues become top tier concerns in addition to the high performance requirement of embedded chips. To leverage limited resources for tiny size chips and overhead cost for complex security mechanisms, we further proposed an advanced IBUS architecture to provide a structural support for the block-based AES algorithm. Our results show that the IBUS based AES-encrypted design costs less in terms of hardware resource and dynamic energy (60.2%), and achieves higher throughput (x1.6) compared with AXI. Effectively dealing with the automation in design and verification for mixed-signal integrated circuits is a critical problem, particularly when the bus architecture is new. Therefore, we further proposed a configurable and synthesizable IBUS design methodology. The flexible structure, together with bus wrappers, direct memory access (DMA), AES engine, memory controller, several mixed-signal verification intellectual properties (VIPs), and bus performance models (BPMs), forms the basic for integrated circuit design, allowing engineers to integrate application-specific modules and other peripherals to create complex SoCs.