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In this thesis we discuss a formal approach to the design of concurrent error detection (CED) logic in field-programmable gate arrays (FPGAs). Single event upsets (SEUs) occurring in look-up table (LUT) configuration bits are considered as the fault model. Our approach involves representing the LUT network of the design implemented in the FPGA with constraints to model the presence of SEUs as a boolean formula in conjunctive normal form. A quantified boolean formula (QBF) based approach to designing CED logic based on parity check codes is found to be infeasible for designs of a realistic size. It is shown that a satisfiability (SAT) solver can be used to find variable assignments that indicate which circuit outputs can be corrupted by upset events in the specified fault model. An algorithm is presented to automatically generate a parity check code, which will identify with one clock cycle detection latency a malfunction caused by an SEU. The resulting parity check logic can be verified using a SAT solver and it is shown to require fewer LUT resources than duplication for most circuits. / Master of Applied Science (MASc)

<p>In design verication, although simulation is still a widely used verication</p> <p>technique in FPGA design, formal verication is obtaining greater acceptance</p> <p>as the complexity of designs increases. In the simulation method, for a circuit</p> <p>with n inputs and m registers an exhaustive test vector will have as many as</p> <p>2^(m+n) elements making it impractical for many modern circuits. Therefore</p> <p>this method is incomplete, i.e., it may fail to catch some design errors due to</p> <p>the lack of complete test coverage. Formal verication can be introduced as a</p> <p>complement to traditional verication techniques.</p> <p>The primary objectives of this thesis are determining: (i) how to for-</p> <p>malize FPGA implementations at dierent levels of abstraction, and (ii) how</p> <p>to prove their functional correctness. This thesis explores two variations of a</p> <p>formal verication framework by proving the functional correctness of several</p> <p>FPGA implementations of commonly used safety subsystem components us-</p> <p>ing the theorem prover PVS. We formalize components at the netlist level and</p> <p>the Verilog Register Transfer HDL level, preserving their functional semantics.</p> <p>Based on these formal models, we prove correctness conditions for the com-</p> <p>ponents using PVS. Finally, we present some techniques which can facilitate</p> <p>the proving process and describe some general strategies which can be used to</p> <p>prove properties of a synchronous circuit design.</p> / Master of Applied Science (MASc)

<p>The number of speed-limiting paths in modern digital integrated circuits (ICs) is in the range of millions. Due to un-modelled electrical effects and process variations in advanced fabrication technologies, it is difficult for pre-silicon timing analysis tools to provide accurate delay estimates. Hence, programmable delay elements are commonly inserted in high-performance circuits in order to provide a tuning mechanism at the post-silicon phase. Due to the large number of such tuning elements, finding the appropriate configuration bits for each element mandates an automated approach.</p> <p>In this thesis we present three contributions to the field of digital IC design automation that leverage the presence of programmable delay tuning elements. These new automated approaches are geared toward three distinct objectives. The first one is to maximize the circuit performance using a scalable algorithmic framework. The second objective is to combat the lifetime performance degradation caused by circuit aging. The final objective is to improve the timing of the scan enable signal during the at-speed testing of digital ICs.</p> <p>As the programmable delay tuning elements will become prevalent in the future generations of digital ICs, the contributions from this thesis will help improve the design methodologies that are expected to evolve in order to address at runtime the timing problems introduced by the increased fabrication process variability.</p> / Doctor of Philosophy (PhD)

Since integration technology is approaching the nanoelectronics range, some practical limits are being reached. Leakage power is increasing more and more with the continuous scaling, and design of clock distribution systems needs to be reconsidered as it becomes difficult to deal with performance and power consumption specifications while keeping a correct synchronisation in modern multi-GHz systems. The ongoing technology trend will become difficult to maintain unless dedicated library cells, new logic styles and circuit methods are emerging to prevent the drawbacks of future nanoscale circuits. In this thesis we investigate a new class of dynamic differential logic family that features a self-timed operation and low output logic swing. The latter contributes to reduce dynamic power, while the self-timing scheme alleviates the drawbacks of synchronous circuits and systems. Furthermore, the dynamic and differential nature of LSCML class brings advantages in terms of reduction of the power consumption variation and thus gives LSCML an additional potential for implementation of secure encryption devices against attacks based on power analysis. We investigate dynamic and leakage power reduction at the cell level through the application of low-power low-voltage techniques to a new hybrid full adder structure. The 8b RCA circuit based on the ULPFA (ultra low power full adder) version of this full adder, achieves a total power and a leakage power, which are both reduced by 50% compared to the 8b RCA implemented with conventional static CMOS full adder, while featuring better power delay product.

Since integration technology is approaching the nanoelectronics range, some practical limits are being reached. Leakage power is increasing more and more with the continuous scaling, and design of clock distribution systems needs to be reconsidered as it becomes difficult to deal with performance and power consumption specifications while keeping a correct synchronisation in modern multi-GHz systems. The ongoing technology trend will become difficult to maintain unless dedicated library cells, new logic styles and circuit methods are emerging to prevent the drawbacks of future nanoscale circuits. In this thesis we investigate a new class of dynamic differential logic family that features a self-timed operation and low output logic swing. The latter contributes to reduce dynamic power, while the self-timing scheme alleviates the drawbacks of synchronous circuits and systems. Furthermore, the dynamic and differential nature of LSCML class brings advantages in terms of reduction of the power consumption variation and thus gives LSCML an additional potential for implementation of secure encryption devices against attacks based on power analysis. We investigate dynamic and leakage power reduction at the cell level through the application of low-power low-voltage techniques to a new hybrid full adder structure. The 8b RCA circuit based on the ULPFA (ultra low power full adder) version of this full adder, achieves a total power and a leakage power, which are both reduced by 50% compared to the 8b RCA implemented with conventional static CMOS full adder, while featuring better power delay product.

This dissertation proposed two time-domain algorithms for extracting the broadband SPICE-compatible models of high-speed coupled interconnects. The first approach is proposed to synthesized the equivalent models of multi-conductor interconnects by cascading multiple configuration-oriented coupled transmission line (CCTL) units. The second approach focuses on the modeling of differential via based on a broadband macro-£k model with three modules represented by the optimum pole-residue forms. Using a systematic lumped-model extraction technique (SLET), all the pole-residue rational functions can transfer into a corresponding lumped model. The accuracy of the two algorithms is demonstrated both in time- and frequency -domain responses comparison with the direct 3D-FDTD simulation.

This dissertation proposed a novel time-domain algorithm for extracting the broadband SPICE-compatible models of power/ground planes with resonance effect. The time-domain algorithm approach can focus on the modeling of interconnectors and power/ground planes based on a broadband macro model. Every module of the broadband macro model is represented by the optimum pole-residue forms. Using a systematic lumped-model extraction technique, all the optimum pole-residue rational functions can be transferred into a corresponding lumped circuit model. The accuracy of the time-domain algorithms is demonstrated both in time- and frequency-domain responses comparison by the 3D-FDTD simulation and measurement. In addition, these models can be efficiently incorporated into the currently available circuit simulator such as HSpice for the consideration of power/ground bouncing noise with active devices in high-speed circuits.

This thesis presents a clockless stochastic low-density parity-check (LDPC) decoder implemented on a Field-Programmable Gate Array (FPGA). Stochastic computing reduces the wiring complexity necessary for decoding by replacing operations such as multiplication and division with simple logic gates. Clockless decoding increases the throughput of the decoder by eliminating the requirement for node signals to be synchronized after each decoding cycle. With this partial-update algorithm the decoder’s speed is limited by the average wire delay of the interleaver rather than the worst-case delay. This type of decoder has been simulated in the past but not implemented on silicon. The design is implemented on an ALTERA Stratix IV EP4SGX230 FPGA and the frame error rate (FER) performance, throughput and power consumption are presented for (96,48) and (204,102) decoders.

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