This thesis presents a clockless stochastic low-density parity-check (LDPC)
decoder implemented on a Field-Programmable Gate Array (FPGA).
Stochastic computing reduces the wiring complexity necessary for
decoding by replacing operations such as multiplication and division with
simple logic gates. Clockless decoding increases the throughput of the
decoder by eliminating the requirement for node signals to be synchronized
after each decoding cycle. With this partial-update algorithm the decoder’s
speed is limited by the average wire delay of the interleaver rather than the
worst-case delay. This type of decoder has been simulated in the past but
not implemented on silicon. The design is implemented on an ALTERA
Stratix IV EP4SGX230 FPGA and the frame error rate (FER) performance,
throughput and power consumption are presented for (96,48) and (204,102)
decoders.
| Identifer | oai:union.ndltd.org:LACETR/oai:collectionscanada.gc.ca:OWTU.10012/8456 |
| Date | January 2014 |
| Creators | Christopher, Ceroici |
| Source Sets | Library and Archives Canada ETDs Repository / Centre d'archives des thèses électroniques de Bibliothèque et Archives Canada |
| Language | English |
| Detected Language | English |
| Type | Thesis or Dissertation |
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