Recent advancements in Large Scale Integration Technology have made available devices, such as microprocessors, analog gates and “three state” logic, that provide the designer with a wide range of possibilities in the design of telecommunication systems. A microprocessor and analog gates are utilized in this design to demonstrate the feasibility of implementing a flexible Telecommunication System. The microprocessor is programmed to control, through software, the system functions. The feasibility of systems highly adaptable to the needs of individual subscribers is thus demonstrated.

<p>This thesis is funded by the IBM Center for Advanced Studies</p> / <p>A large number of scientific applications rely on the computing of logarithm. Thus, accelerating the speed of computing logarithms is significant and necessary. To this end, we present the realization of a pipelined Logarithm Computation Unit (LCU) in hardware that uses lookup table and interpolation techniques. The presented LCU supports single precision arithmetic with fixed accuracy and speed. We estimate that it can generate 2.9G single precision values per second under a 65nm fabrication process. In addition, the accuracy is at least 21 bits while lookup table size is about 7.776KB. To the best of our knowledge, our LCU achieves the fastest speed at its current accuracy and table size.</p> / Master of Science (MSc)

This thesis describes an all-in-one flight control system (FCS) that was designed for unmanned aerial vehicles (UAVs). The project focuses on the embedded hardware aspect of a stand-alone system with low-cost and reliability in mind.

Turbo códigos têm se tornado um importante ramo na pesquisa de codificação de canal e já foram adotados como padrão para a terceira geração de comunicação móvel. Devido ao seu alto ganho de codificação, os turbo códigos são vistos como fortes candidatos a serem adotados como padrão das futuras gerações de redes sem fio. Esse esquema de codificação é baseado na decodificação iterativa, onde decodificadores de entrada e saída suaves produzem refinamento da informação a cada iteração. Essa dissertação apresenta resultados de um estudo comparativo entre dois esquemas de codificação: turbo códigos de bloco e turbo códigos convolucionais. Os resultados mostram que os dois esquemas de codificação têm desempenho funcional complementar, sendo importante a especificação de um alvo em termos de relação sinal/ruído ou taxa de erro de bits para a escolha do esquema de codificação mais adequado. Com o mesmo modelo em linguagem de programação C foi feita uma exploração do algoritmo visando diminuição do consumo de potência. Essa exploração em parte foi feita segundo uma metodologia de exploração sistemática das possibilidades de transferência e armazenamento de dados (DTSE). Com a exploração, a redução total de consumo de potência para o armazenamento de dados foi estimada em 34%. / Turbo codes have become an important branch on channel coding research and have been adopted as standard in the third generation of mobile communication systems. Due to their high coding gain, turbo codes are expected to be part of the next generations of wireless networks standards. This coding scheme is based on iterative decoding, as soft input/soft output decoders produce an information refinement in each iteration. This dissertation shows the results of a comparative performance study of two different turbo coding schemes: block turbo codes and convolutional turbo codes. The results obtained show that the two schemes have complementary performance. It is necessary to specify a target in terms of bit error rate or signal/noise ratio. With the same C model an exploration aiming at reducing power consumption was done. Part of this exploration was done following a systematic methodology of data transfer and storage exploration (DTSE). With this exploration, a reduction of 34% on power consumption was estimated.

Este trabalho consiste no estudo e projeto de circuitos Dual-Modulus Prescaler utilizados em sistemas de comunicação RF (radio frequency). Sistemas de comunicação RF trabalham em bandas de freqüência pré-definidas e dentro destas há, normalmente, vários canais para transmissão. Neste caso, decidido o canal onde se vai trabalhar, o receptor e o transmissor geram, através de um circuito chamado Sintetizador de Freqüências, sinais que têm a freqüência igual a freqüência central do canal utilizado. Esses sinais ou tons são empregados na modulação e demodulação das informações transmitidas ou recebidas. O Sintetizador de Freqüências possui como componentes um oscilador controlável, contadores programáveis, comparadores de fase e um divisor de freqüências chamado Dual-Modulus Prescaler. O funcionamento do Sintetizador é descrito a seguir: o Prescaler recebe um sinal proveniente da saída do oscilador controlável e gera um sinal que tem a freqüência igual a aquela do sinal de entrada dividida por N ou N+1, dependendo do valor lógico de um sinal de controle. O sinal gerado por esse circuito divisor será ainda dividido por contadores e comparado a um sinal de referência externo no comparador de fase. O comparador, por sua vez, gera o sinal de controle do oscilador controlável, aumentando ou reduzindo sua velocidade. Pelo ajuste do número de vezes que o circuito Prescaler divide por N ou N+1, se controla a freqüência da saída do Sintetizador. De todos os circuitos que compõe o Sintetizador de Freqüência, apenas o oscilador controlável e o Prescaler trabalham em altas freqüências (freqüência máxima do sistema) e por conseqüência, a velocidade máxima de trabalho e o consumo de potência do Sintetizador dependerão da performance destes. Neste trabalho se utilizou a técnica Extended True Single Clock Phase para se projetar o Prescaler. O projeto do circuito Prescaler foi realizado na tecnologia CMOS (Complementary Metal Oxide Silicon) 0,35 ?m da AMS [Au03a], que satisfaz as necessidades visadas (banda de trabalho centrada em 2,4 GHz) e tem um custo para prototipagem satisfatório. Vários circuitos foram implementados nesta tecnologia e testados, se obtendo um Prescaler que atinge velocidade de 3,6 GHz, consumo de 1,6 mW para tensão de alimentação de 3,3 V. / This work consists of the study and project of circuits Dual-Modulus Prescaler used in communication systems RF (radio frequency). RF Communication Systems work in predefined frequency bands and inside of them, there are several transmission channels. In this case, once decided the channel where we will work, the receiver and the transmitter generate, through a circuit called Frequency Synthesizer, signs that have the same frequency of the central frequency of the used channel. Those signs or tones are used in the modulation and demodulation of the transmitted or received information. The Frequency Synthesizer possesses as components a controllable oscillator, programmable counters, phase comparator and a frequency divider called Dual-Modulus Prescaler. The Synthesizer operation is described: the Prescaler receives a sign from the oscillator and generates an output signal with frequency equal to the frequency of the input signal divided by N or N+1, depending on the logical value of a control sign. The output of the Prescaler will be divided by other counters and compared with an external reference sign in the phase comparator. That comparator, for its turn, generates a control signal for the oscillator, increasing or reducing its speed. By the adjustment of the number of times that the circuit Prescaler divides for N or N+1, the frequency of Synthesizer output is controlled. From all the blocks that compose the Frequency Synthesizer, only the controllable oscillator and the Prescaler work in high frequencies (the maximum frequency of the system), and, in consequence, the maximum speed and the power consumption of the full Synthesizer will depend on the performance of these two blocks. In this work we applied the technique called Extended True Single Clock Phase to design the Prescaler. The project of the circuit Prescaler used the technology CMOS (Complementary Metal Oxide Silicon) 0.35 ?m of AMS [Au03a]. This technology was used because it satisfies the sought needs (work band centered in 2.4 GHz) and has a satisfactory cost. Several circuits were implemented in this technology and tested and it was obtained a Prescaler which reaches 3.6 GHz, 1.6 mW power consumption with power supply of 3.3 V.

Non traduit / Semiconductor is one of the most reliable inventions when engineered and used with longevity in mind. However, the increasing demand of fast and highly featured products has drastically changed the reliability realm in the recent years. The means of improving the reliability of nano-metric technology circuits encompass techniques that tackle reliability issues at the level of technology, design and manufacturing. Absolutely necessary but these techniques are almost inevitably imperfect. Therefore, it becomes essential to reduce the consequence of the "remaining" faults using fault tolerance techniques.This thesis focuses on improving and developing new low-power fault tolerance techniques that combine the attractive features of different types of redundancies to tackle permanent and transient faults and addresses the problem of error detection and confinement in modern microprocessor cores. Our case study implementation results show that a power saving of up to 20% can be achieved in comparison with fault tolerance techniques that use only one type of redundancy, and offer low-power lifetime reliability improvement.With the objective to further improve the efficiency in terms of cost and fault tolerance capability we present a design space exploration and an efficient cost-reliability trade-off analysis methodology to selectively harden logic circuits using hybrid fault tolerant techniques. The outcome of the two studies establish that hybrid fault tolerant approaches provide a good foundation for building low-power reliable circuits and systems from future technologies, and our experimental results set a good starting point for further innovative research in this area.

Turbo códigos têm se tornado um importante ramo na pesquisa de codificação de canal e já foram adotados como padrão para a terceira geração de comunicação móvel. Devido ao seu alto ganho de codificação, os turbo códigos são vistos como fortes candidatos a serem adotados como padrão das futuras gerações de redes sem fio. Esse esquema de codificação é baseado na decodificação iterativa, onde decodificadores de entrada e saída suaves produzem refinamento da informação a cada iteração. Essa dissertação apresenta resultados de um estudo comparativo entre dois esquemas de codificação: turbo códigos de bloco e turbo códigos convolucionais. Os resultados mostram que os dois esquemas de codificação têm desempenho funcional complementar, sendo importante a especificação de um alvo em termos de relação sinal/ruído ou taxa de erro de bits para a escolha do esquema de codificação mais adequado. Com o mesmo modelo em linguagem de programação C foi feita uma exploração do algoritmo visando diminuição do consumo de potência. Essa exploração em parte foi feita segundo uma metodologia de exploração sistemática das possibilidades de transferência e armazenamento de dados (DTSE). Com a exploração, a redução total de consumo de potência para o armazenamento de dados foi estimada em 34%. / Turbo codes have become an important branch on channel coding research and have been adopted as standard in the third generation of mobile communication systems. Due to their high coding gain, turbo codes are expected to be part of the next generations of wireless networks standards. This coding scheme is based on iterative decoding, as soft input/soft output decoders produce an information refinement in each iteration. This dissertation shows the results of a comparative performance study of two different turbo coding schemes: block turbo codes and convolutional turbo codes. The results obtained show that the two schemes have complementary performance. It is necessary to specify a target in terms of bit error rate or signal/noise ratio. With the same C model an exploration aiming at reducing power consumption was done. Part of this exploration was done following a systematic methodology of data transfer and storage exploration (DTSE). With this exploration, a reduction of 34% on power consumption was estimated.

A diminuição das dimensões do transistor MOS tem sido a principal estratégia adotada para alcançar otimizações de desempenho na fabricação de circuitos integrados. Contudo, reduzir as dimensões dos transistores tem se tornado uma tarefa cada vez mais difícil de ser alcançada. Nesse contexto, vários esforços estão sendo feitos para encontrar dispositivos alternativos que permitam futuros avanços em relação à capacidade computacional. Entre as mais promissoras tecnologias emergentes estão os transistores de efeito de campo com múltiplos e independentes gates (MIGFETs). MIGFETs são dispositivos controlados por mais que um terminal de controle permitindo que funções Booleanas com mais de uma variável sejam implementadas por um único dispositivo. Redes de chaves construídas com dispositivos MIGFET tendem a ser mais compactas do que as redes de chaves tradicionais. No entanto existe um compromisso em relação a redução no número de chaves, devido à maior capacidade lógica, e um maior tamanho e pior desempenho do dispositivo. Neste trabalho, pretendemos explorar tal balanceamento no sentido de avaliar os impactos do uso de MIGFETs na construção de circuitos integrados digitais. Dessa forma, alguns critérios de avaliação são apresentados no sentido de analisar área e atraso de circuitos construídos a partir de dispositivos MIGFET, onde cada transistor é representado por um modelo RC. Em particular, tal avaliação de área e desempenho é aplicada no projeto de circuitos somadores binários específicos (metodologia full-custom). Além do mais, bibliotecas de células construídas a partir de dispositivos MIGFET são utilizadas na síntese automática de circuitos de referência através da metodologia standard-cell. Através dos experimentos, é possível ter-se uma ideia, mesmo que inicial e pessimista, do quanto o layout de um dado MIGFET pode ser maior do que um single-gate FinFET e ainda apresentar redução na área do circuito devido à compactação lógica. / The scaling of MOS transistor has been the main manufacturing strategy for improving integrated circuit (IC) performance. However, as the device dimensions shrink, the scaling becomes harder to be achieved. In this context, much effort has been done in order to develop alternative devices that may allow further progress in computation capability. Among the promising emerging technologies is the multiple independent-gate field effect transistors (MIGFETs). MIGFETs are switch-based devices, which allow more logic capability in a single device. In general, switch networks built through MIGFET devices tend to be more compact than the traditional switch networks. However, there is a tradeoff between the number of logic switches merged and the area and performance of a given MIGFET. Thus, we aim to explore such a tradeoff in order to evaluate the MIGFET impacts in the building digital integrated circuits. To achieve this goal, in this work, we present an area and performance evaluation based on digital circuit built using MIGFET devices, where each MIGFET is represented through RC modelling. In particular, such an evaluation is applied on full-custom design of binary adder circuits and on standard-cell design flow targeting in a set of benchmark circuits. Through the experiments, it is possible have an insight, even superficial and pessimist, about how big can be the layout of a given MIGFET than the single-gate FinFET and still show a reduction in the final circuit area due to the logic compaction.

Many modern computer systems are distributed over space. Well-known examples are the Internet of Things and IBM's TrueNorth for deep learning applications. At the Asynchronous Research Center (ARC) at Portland State University we build distributed hardware systems using self-timed computation and delay-insensitive communication. Where appropriate, self-timed hardware operations can reduce average and peak power, energy, latency, and electromagnetic interference. Alternatively, self-timed operations can increase throughput, tolerance to delay variations, scalability, and manufacturability. The design of complex hardware systems requires design automation and support for test, debug, and product characterization. This thesis focuses on design compilation and test support for dataflow applications. Both parts are necessary to go from self-timed circuits to large-scale hardware systems. As part of the research in design compilation, the ARCwelder compiler designed by Willem Mallon (previously with NXP and Philips Handshake Solutions) was extended. The key to testing distributed systems, including self-timed systems, is to identify the actions in the systems. In distributed systems there is no such thing as a global action. To test, debug, characterize, and even initialize distributed systems, it is necessary to control the local actions. The designs developed at the ARC separate the actions from the states ab initio. As part of the research in test and debug, a special circuit to control actions, called MrGO, was implemented. A scan and JTAG test interface was also implemented. The test implementations have been built into two silicon test experiments, called Weaver and Anvil, and were used successfully for testing, debug, and performance characterizations.

Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes. One of the more essential concepts for achieving this goal is the notion of resilient and survivable digital I&C systems. In recent years, self-healing concepts based on biological physiology have received attention for the design of robust digital systems. However, many of these approaches have not been architected from the outset with safety in mind, nor have they been targeted for the automation community where a significant need exists. This dissertation presents a new self-healing digital I&C architecture called BioSymPLe, inspired from the way nature responds, defends and heals: the stem cells in the immune system of living organisms, the life cycle of the living cell, and the pathway from Deoxyribonucleic acid (DNA) to protein. The BioSymPLe architecture is integrating biological concepts, fault tolerance techniques, and operational schematics for the international standard IEC 61131-3 to facilitate adoption in the automation industry. BioSymPLe is organized into three hierarchical levels: the local function migration layer from the top side, the critical service layer in the middle, and the global function migration layer from the bottom side. The local layer is used to monitor the correct execution of functions at the cellular level and to activate healing mechanisms at the critical service level. The critical layer is allocating a group of functional B cells which represent the building block that executes the intended functionality of critical application based on the expression for DNA genetic codes stored inside each cell. The global layer uses a concept of embryonic stem cells by differentiating these type of cells to repair the faulty T cells and supervising all repair mechanisms. Finally, two industrial applications have been mapped on the proposed architecture, which are capable of tolerating a significant number of faults (transient, permanent, and hardware common cause failures CCFs) that can stem from environmental disturbances and we believe the nexus of its concepts can positively impact the next generation of critical systems in the automation industry.