Thesis (Ph.D)--Stanford University, 1999. / Title from metadata (viewed May 9, 2002). "August 1999." "Adminitrivia V1/Prg/19990823"--Metadata.

Thesis (Ph. D.)--University of Oregon, 2006. / Typescript. Includes vita and abstract. Includes bibliographical references (leaves 150-162). Also available for download via the World Wide Web; free to University of Oregon users.

Computer has evolved rapidly during the past several decades in terms of its implementation technology; it's architecture, however, has not changed dramatically since the von Neumann computer(control flow) model emerged in the 1940s. One main reason is that the performance for this kind of computers was able to satisfy the requirement of most users. Another reason maybe that the engineers who designed them are more familiar with this model. However, recent solutions to the problem of parallelizing sequential nature instructions on a von Neumann machine complicate both the compiler and the controller design. Therefore, another computer model, namely the data flow model, has regained attention since this model of computation exposes parallelism inherent in the program naturally. In terms of implementation methodology, we currently use synchronous sequential logic, which is clock controlled for synchronization within circuits. This design philosophy becomes hard to follow due to the occurrence of clock skew as the clock frequency goes higher and higher. One way to eliminate these clock related problems is to use the self-timed(asynchronous) implementation methodology. It features advantages such as free of clock-skew, low power consumption, composibility and so forth. Since data flow(data driven) computation model provides the execution of instructions asynchronously, it is natural to implement a data flow processor using self-timed circuits. In this thesis, micro pipelines, one of the self-timed implementation methodology, is used to implement a preliminary version of general purpose static data flow processor. Some interesting observations will be addressed in this thesis. An example program of general difference recursive equation is given to test the correctness and performance of this processor. We hope to gain more insight on how to design and implement self-timed systems in the future. / Graduation date: 1994

Not available

Thesis (Ph. D.)--University of Texas at Austin, 2007. / Vita. Includes bibliographical references and index.

Written for the School of Computer Science. Title from title page of PDF (viewed 2009/013/09). Includes bibliographical references.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. / Panagiotis Manolios, Committee Member ; Douglas M. Blough, Committee Member ; Vincent John Mooney III, Committee Chair ; William D. Hunt, Committee Member ; Sung Kyu Lim, Committee Member. Vita. Includes bibliographical references.

Thesis (Ph.D)--Computing, Georgia Institute of Technology, 2009. / Committee Chair: Ramachandran, Umakishore; Committee Member: Knobe Kathleen; Committee Member: Pande, Santosh; Committee Member: Prvulovic, Milos; Committee Member: Rehg, James M.. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (Ph. D.)--Ohio State University, 2005. / Title from first page of PDF file. Document formatted into pages; contains xiv, 126 p.; also includes graphics. Includes bibliographical references (p. 119-126). Available online via OhioLINK's ETD Center

Thesis (Ph. D.)--Georgia Institute of Technology, 2004. / Vita. Department of Electrical and Computer Engineering, Georgia Institute of Technology. Includes bibliographical references (p. 142-146).