Productivity for digital circuit design is being outpaced currently by the rate at which<br />silicon is growing such as FPGAs. Complex designs take a large amount of engineering<br />hours to complete. Reuse of existing design can potentially decrease this cost and increase<br />design productivity. However, existing digital hardware designs are not being effectively<br />reused by the hardware community due to the inability of designers to have knowledge of<br />all the attributes of designs that can be reused. In addition, designers will have to accustom<br />themselves to designs in the hardware library. By having a back-end system that looks for<br />similar circuits, there is little to no effort for the designer to reuse the design. This thesis<br />provides an overview and comparison of different methods for characterizing and comparing<br />digital circuits in order to suggest candidate circuits that engineers can reuse. Several of<br />these methods are implemented, modified, and compared to show the feasibility of utilizing<br />this work for increasing overall productivity.<br /> / Master of Science

A DRAM communicates with a processing unit via two interfaces: a data interface and a command interface. In today's DRAMs, also known as synchronous DRAMs (SDRAMs), both interfaces use a clock to communicate with the processing unit. The clock times the communication between the processing unit and the SDRAM on both the data interface and the command interface. We propose a self-timed DRAM. The self-timed DRAM introduces more flexibility into the DRAM interface by eliminating the clock. The command interface and the data interface each communicate with the processing unit using a handshake protocol rather than a clock. This thesis presents the data interface between the self-timed DRAM and the processing unit. The proposed data interface is self-timed. The self-timed data interface allows the DRAM to deliver data to or accept data from the processing unit as the processing unit demands rather than on a schedule set from the command interface. The self-timed data interface is designed using GasP circuits and micropipeline circuits. The design is simulated in 180nm CMOs process technology using hspice. This thesis presents the effects of width mismatch on the self-timed data interface. The micropipeline is slightly faster than the GasP. Also, the thesis compares the self-timed DRAM data interface with synchronous DRAM for the data burst rate.

[pt] O trabalho realizado visa auxiliar o projeto de circuitos digitais, verificar o funcionamento de sua lógica, e servir como ferramenta para obtenção de seqüências de teste. Ele consiste de uma simulação, via computador, de circuitos digitais, contendo integrados MSI`s e SSI`s, descritos em nível de porta pela linguagem de programação PL/I. os integrados são descritos segundo os esquemas dos seus fabricantes. Objetivou-se, principalmente, realizar uma simulação que verificasse a capacidade de deteção de uma seqüência de vetores de entrada, que tivesse uma boa performance em termos de tempo e memória de computador, e que fosse facilmente utilizada. A simulação é aplicável a circuitos combinacionais, e a circuitos seqüenciais que comportem-se sincronamente. / [en] The present work was realied as na to the design of digital circuits, verification of teir logic, and to serve as a tool for the feneration of test sequences. It consists of a digital computer simulation of digital circuits, which contrain SSI`s and MSI`s, described at the gate level by the programming language PL/I. The integrated circuits are described according to the specifications used in the manufacturer`s catalogs. The principle objective was to realize a simulation easy to be used, that would verify the ability of a given sequance of input vectors to detect the faults of a logic circuit, and would have a good performance in terms of computer time and memory required. The simulaation is applicable to both combinational circuits and to sequantial circuits that behave synchronously.

The application of adaptive communication techniques for mobile communications has attracted considerable interest in the last decade. One example of these techniques is spatial filtering through planar antenna array beam forming. This thesis describes the development of a digital system that adaptively controls a phased array antenna. The radiating structure of the phased antenna array is tetrahedral-shaped and contains four antenna elements on each of its three faces. The overall system comprises of a digital control board with an external computer interface, an RF control board, and the phased antenna array. The RF controls the main lobe direction on the phased array antenna. This thesis describes the design and implementation of the digital control board. The digital control board`s primary responsibilities are implementing inter- faces between the external computer and the RF board, which results in two operational modes: the MATLAB graphical user interface (GUI) mode and the adaptive receive mode. The GUI mode allows users to input parameters that provide interactive control of the phased antenna array by interfacing with an external computer and the RF control board. The adaptive receive mode im- plements an algorithm for an adaptive receive station. This algorithm uses a 58-point scanning technique that locates the maximum receive power direction. Test results show that the digital control board successfully manages the RF board control voltage with an nominal error of less than 1%, which subsequently allows for precise control of the antenna`s active face. Additionally, testing of the GUI demonstrated the successful interactive application of various system control parameters.

No description available.

This study comprises two tasks. The first is to implement gate-level circuit camouflage techniques. The second is to implement the Oracle-guided incremental de-camouflage algorithm and apply it to the camouflaged designs. The circuit camouflage algorithms are implemented in Python, and the Oracle- guided incremental de-camouflage algorithm is implemented in C++. During this study, I evaluate the Oracle-guided de-camouflage tool (Solver, in short) performance by de-obfuscating the ISCAS-85 combinational benchmarks, which are camouflaged by the camouflage algorithms. The results show that Solver is able to efficiently de-obfuscate the ISCAS-85 benchmarks regardless of camouflaging style, and is able to do so 10.5x faster than the best existing approaches. And, based on Solver, this study also measures the de-obfuscation runtime for each camouflage style.

The topics described in this diploma thesis belong to the area of digital systems testability analysis. Basic concepts as dependability, controllability, observability and testability are explained. Methods of raising testability and dependability of digital circuits are mentioned including the metrics which allow to evaluate testability parameters. Furthermore, the thesis describes the formal model of digital systems which introduces the implementing part of the thesis. Within this part, a program tool is demonstrated, which allows to identify the components of digital circuits and their function. The other function of the program tool is to create control circuits that check the correct function of such digital circuits.

Primitivas criptografias assimétricas são essenciais para conseguir comunicação segura numa rede ou meio público. Essas primitivas podem ser instaladas como bibliotecas de software ou como coprocessadores de hardware. Coprocessadores de hardware são muito utilizados em cenários como Systems on Chip (SoC), dispositivos embarcados ou servidores de aplicações específicas. Coprocessadores existentes baseados em RSA ou curvas ellipticas (ECC) fazem um processamento intenso por causa da aritmética modular de grande precisão, portanto não estão disponíveis em plataformas com quantidade de energia mais restrita. Para prover primitivas assimétricas para esses dispositivos, será avaliado um esquema de cifração assimétrica que utiliza artimética de pequena precisão, chamado McEliece. McEliece foi proposto com códigos de Goppa binários durante o mesmo ano que o RSA, porém com chaves públicas 50 vezes maiores. Por causa de chaves tão grandes ele não ganhou muita atenção como RSA e ECC. Com a adoção de códigos Quase-Diádicos de Goppa binários é possível obter níveis de segurança práticos com chaves relativamente pequenas. Para avaliar uma implementação em hardware para esse esquema, foi proposto uma arquitetura escalável que pode ser configurada de acordo com os requisitos do projeto. Essa arquitetura pode ser utilizada em todos os níveis de segurança, de 80 até 256 bits de segurança, da menor unidade até as maiores. Nossa arquitetura foi implementada na família de FPGAs Spartan 3 para códigos de Goppa binários, onde foi possível decifrar em 5854 ciclos com 4671 Slices, enquanto que na literatura os melhores resultados obtidos são de 10940 ciclos para 7331 Slices. / Asymmetric cryptographic primitives are essential to enable secure communications on public networks or public mediums. These cryptographic primitives can be deployed as software libraries or hardware coprocessors. Hardware coprocessors are mostly employed in Systems on Chip (SoC) scenarios, embedded devices, or application-specific servers. Available solutions based on RSA or Elliptic Curve Cryptography (ECC) are highly processing intensive because of the underlying extended precision modular arithmetic, and hence they are not available on the most energy constrained platforms. To provide asymmetric primitives in those restricted devices, we evaluate another asymmetric encryption scheme implementable with lightweight arithmetic, called McEliece. McEliece was proposed with binary Goppa codes during same year of RSA with public keys 50 times larger. Because of such large keys it has not gained as much attention as RSA or ECC. With the adoption of binary Quasi- Dyadic Goppa (QD-Goppa) codes it is possible to attain practical security levels with reasonably small keys. To evaluate a hardware implementation of this scheme, we investigate a scalable architecture that can be reconfigured according to project requirements. This architecture is suitable for all usual security levels, from 80 to 256-bit security, from the smallest unit to bigger ones. With our architecture implemented on a Spartan 3 FPGA for binary Goppa codes it is possible to decrypt in 5854 cycles with 4671 Slices, whilst in literature best results were in 10940 cycles with 7331 Slices.

Primitivas criptografias assimétricas são essenciais para conseguir comunicação segura numa rede ou meio público. Essas primitivas podem ser instaladas como bibliotecas de software ou como coprocessadores de hardware. Coprocessadores de hardware são muito utilizados em cenários como Systems on Chip (SoC), dispositivos embarcados ou servidores de aplicações específicas. Coprocessadores existentes baseados em RSA ou curvas ellipticas (ECC) fazem um processamento intenso por causa da aritmética modular de grande precisão, portanto não estão disponíveis em plataformas com quantidade de energia mais restrita. Para prover primitivas assimétricas para esses dispositivos, será avaliado um esquema de cifração assimétrica que utiliza artimética de pequena precisão, chamado McEliece. McEliece foi proposto com códigos de Goppa binários durante o mesmo ano que o RSA, porém com chaves públicas 50 vezes maiores. Por causa de chaves tão grandes ele não ganhou muita atenção como RSA e ECC. Com a adoção de códigos Quase-Diádicos de Goppa binários é possível obter níveis de segurança práticos com chaves relativamente pequenas. Para avaliar uma implementação em hardware para esse esquema, foi proposto uma arquitetura escalável que pode ser configurada de acordo com os requisitos do projeto. Essa arquitetura pode ser utilizada em todos os níveis de segurança, de 80 até 256 bits de segurança, da menor unidade até as maiores. Nossa arquitetura foi implementada na família de FPGAs Spartan 3 para códigos de Goppa binários, onde foi possível decifrar em 5854 ciclos com 4671 Slices, enquanto que na literatura os melhores resultados obtidos são de 10940 ciclos para 7331 Slices. / Asymmetric cryptographic primitives are essential to enable secure communications on public networks or public mediums. These cryptographic primitives can be deployed as software libraries or hardware coprocessors. Hardware coprocessors are mostly employed in Systems on Chip (SoC) scenarios, embedded devices, or application-specific servers. Available solutions based on RSA or Elliptic Curve Cryptography (ECC) are highly processing intensive because of the underlying extended precision modular arithmetic, and hence they are not available on the most energy constrained platforms. To provide asymmetric primitives in those restricted devices, we evaluate another asymmetric encryption scheme implementable with lightweight arithmetic, called McEliece. McEliece was proposed with binary Goppa codes during same year of RSA with public keys 50 times larger. Because of such large keys it has not gained as much attention as RSA or ECC. With the adoption of binary Quasi- Dyadic Goppa (QD-Goppa) codes it is possible to attain practical security levels with reasonably small keys. To evaluate a hardware implementation of this scheme, we investigate a scalable architecture that can be reconfigured according to project requirements. This architecture is suitable for all usual security levels, from 80 to 256-bit security, from the smallest unit to bigger ones. With our architecture implemented on a Spartan 3 FPGA for binary Goppa codes it is possible to decrypt in 5854 cycles with 4671 Slices, whilst in literature best results were in 10940 cycles with 7331 Slices.

The main issue in this thesis is to minimize the energy consumption per operation for the arithmetic parts of DSP circuits, such as digital filters. More specific, the focus is on single- and multiple-constant multiplications, which are realized using shift-and-add based computations. The possibilities to reduce the complexity, i.e., the chip area, and the energy consumption are investigated. Both serial and parallel arithmetic are considered. The main difference, which is of interest here, is that shift operations in serial arithmetic require flip-flops, while shifts can be hardwired in parallel arithmetic.The possible ways to connect a given number of adders is limited. Thus, for single-constant multiplication, the number of shift-and-add structures is finite. We show that it is possible to save both adders and shifts compared to traditional multipliers. Two algorithms for multiple-constant multiplication using serial arithmetic are proposed. For both algorithms, the total complexity is decreased compared to one of the best-known algorithms designed for parallel arithmetic. Furthermore, the impact of the digit-size, i.e., the number of bits to be processed in parallel, is studied for FIR filters implemented using serial arithmetic. Case studies indicate that the minimum energy consumption per sample is often obtained for a digit-size of around four bits.The energy consumption is proportional to the switching activity, i.e., the average number of transitions between the two logic levels per clock cycle. To achieve low power designs, it is necessary to develop accurate high-level models that can be used to estimate the switching activity. A method for computing the switching activity in bit-serial constant multipliers is proposed.For parallel arithmetic, a detailed complexity model for constant multiplication is introduced. The model counts the required number of full and half adder cells. It is shown that the complexity can be significantly reduced by considering the interconnection between the adders. A main factor for energy consumption in constant multipliers is the adder depth, i.e., the number of cascaded adders. The reason for this is that the switching activity will increase when glitches are propagated to subsequent adders. We propose an algorithm, where all multiplier coefficients are guaranteed to be realized at the theoretically lowest depth possible. Implementation examples show that the energy consumption is significantly reduced using this algorithm compared to solutions with fewer word level adders.For most applications, the input data are correlated since real world signals are processed. A data dependent switching activity model is derived for ripple-carry adders. Furthermore, a switching activity model for the single adder multiplier is proposed. This is a good starting point for accurate modeling of shift-and-add based computations using more adders.Finally, a method to rewrite an arbitrary function as a sum of weighted bit-products is presented. It is shown that for many elementary functions, a majority of the bit-products can be neglected while still maintaining reasonable high accuracy, since the weights are significantly smaller than the allowed error. The function approximation algorithms can be implemented using a low complexity architecture, which can easily be pipelined to an arbitrary degree for increased throughput.