Στόχος μου ήταν να αναφέρω τις βασικές μεθόδους βελτιστοποίησης της επιφάνειας και της καθυστέρησης ενός FIR φίλτρου σταθερών συντελεστών που έχουν προταθεί τα τελευταία χρόνια, να υλοποιήσω τις μεθόδους βελτιστοποίησης της επιφάνειας και να παραθέσω τα αποτελέσματα εξομοίωσης των παραπάνω μεθόδων. / My aim was to present the basic methods of reducing the area and delay of FIR filters of constant coefficients, to create the methods of reducing the area of FIR filters and to compare these methods.

Υλοποίηση παραμετροποιημένων FIR φίλτρων με την βοήθεια της γλώσσας περιγραφής υλικού VHDL. Μελέτη των αποτελεσμάτων για χώρο και περιοχή που καταλαμβάνει ο σχεδιαμσός. / FIR implementation with the description language VHDL. We discuss their results for area and the delay of each diagram (FIR filter).

This thesis presents a linear phase finite impulse response filter implementation developed on a custom computing platform called WILDFORCE. The work has been motivated by ways to off-load intensive computing tasks to hardware for indoor communications channel modeling. The design entails complex convolution filters with customized lengths that can support channel impulse response profiles generated by SIRCIM. The paper details the partitioning for a fully pipelined convolution algorithm onto field programmable gate arrays through VHDL synthesis. Using WILDFORCE, the filter can achieve calculations at 160 MFLOPs/s. / Master of Science

<p>FIR filters are widely used nowadays, with applications from MP3 players, Hi-Fi systems, digital TVs, etc. to communication systems like wireless communication. They are implemented in DSPs and there are several trade-offs that make important to have an exact as possible estimation of the required filter order. </p><p>In order to find a better estimation of the filter order than the existing ones, genetic expression programming (GEP) is used. GEP is a Genetic Algorithm that can be used in function finding. It is implemented in a commercial application which, after the appropriate input file and settings have been provided, performs the evolution of the individuals in the input file so that a good solution is found. The thesis is the first one in this new research line. </p><p>The aim has been not only reaching the desired estimation but also pave the way for further investigations.</p>

<p>The main issue in this thesis is to minimize the energy consumption per operation for the arithmetic parts of DSP circuits, such as digital filters. More specific, the focus is on single- and multiple-constant multiplication using serial arithmetic. The possibility to reduce the complexity and energy consumption is investigated. The main difference between serial and parallel arithmetic, which is of interest here, is that a shift operation in serial arithmetic require a flip-flop, while it can be hardwired in parallel arithmetic.</p><p>The possible ways to connect a certain number of adders is limited, i.e., for single-constant multiplication, the number of possible structures is limited for a given number of adders. Furthermore, for each structure there is a limited number of ways to place the shift operations. Hence, it is possible to find the best solution for each constant, in terms of complexity, by an exhaustive search. Methods to bound the search space are discussed. We show that it is possible to save both adders and shifts compared to CSD serial/parallel multipliers. Besides complexity, throughput is also considered by defining structures where the critical path, for bit-serial arithmetic, is no longer than one full adder.</p><p>Two algorithms for the design of multiple-constant multiplication using serial arithmetic are proposed. The difference between the proposed design algorithms is the trade-offs between adders and shifts. For both algorithms, the total complexity is decreased compared to an algorithm for parallel arithmetic.</p><p>The impact of the digit-size, i.e., the number of bits to be processed in parallel, in FIR filters is studied. Two proposed multiple-constant multiplication algorithms are compared to an algorithm for parallel arithmetic and separate realization of the multipliers. The results provide some guidelines for designing low power multiple-constant multiplication algorithms for FIR filters implemented using digit-serial arithmetic.</p><p>A method for computing the number of logic switchings in bit-serial constant multipliers is proposed. The average switching activity in all possible multiplier structures with up to four adders is determined. Hence, it is possible to reduce the switching activity by selecting the best structure for any given constant. In addition, a simplified method for computing the switching activity in constant serial/parallel multipliers is presented. Here it is possible to reduce the energy consumption by selecting the best signed-digit representation of the constant.</p><p>Finally, a data dependent switching activity model is proposed for ripple-carry adders. For most applications, the input data is correlated, while previous estimations assumed un-correlated data. Hence, the proposed method may be included in high-level power estimation to obtain more accurate estimates. In addition, the model can be used as cost function in multiple-constant multiplication algorithms. A modified model based on word-level statistics, which is accurate in estimating the switching activity when real world signals are applied, is also presented.</p> / Report code: LiU-Tek-Lic-2006:30.

Implementation of the polyphase decomposed FIR filter structure involves two steps; the generation of the partial products and the efficient reduction of the generated partial products. The partial products are generated by a constant multiplication of the filter coefficients with the input data and the reduction of the partial products is done by building a pipelined adder tree using FAs and HAs. To improve the speed and to reduce the complexity of the reduction tree a4:2 counter is introduced into the reduction tree. The reduction tree is designed using a bit-level optimized ILP problem which has the objective function to minimize the overall cost of the hardware used. For this purpose the layout design for a 4:2 counter has been developed and the cost function has been derived by comparing the complexity of the design against a standard FA design. The layout design for a 4:2 counter is implemented in a 65nm process using static CMOS logic style and DPL style. The average power consumption drawn from a 1V power supply, for the static CMOS design was found to be 16.8μWand for the DPL style it was 12.51μW. The worst case rise or fall time for the DPL logic was 350ps and for the static CMOS logic design it was found to be 260ps. The usage of the 4:2 counter in the reduction tree infused errors into the filter response, but it helped to reduce the number of pipeline stages and also to improve the speed of the partial product reduction.

FIR filters are widely used nowadays, with applications from MP3 players, Hi-Fi systems, digital TVs, etc. to communication systems like wireless communication. They are implemented in DSPs and there are several trade-offs that make important to have an exact as possible estimation of the required filter order. In order to find a better estimation of the filter order than the existing ones, genetic expression programming (GEP) is used. GEP is a Genetic Algorithm that can be used in function finding. It is implemented in a commercial application which, after the appropriate input file and settings have been provided, performs the evolution of the individuals in the input file so that a good solution is found. The thesis is the first one in this new research line. The aim has been not only reaching the desired estimation but also pave the way for further investigations.

Στην παρούσα διπλωματική εργασία μελετήθηκε και κατασκευάστηκε ένα σύστημα προσομοίωσης και εξομοίωσης των χαρακτηριστικών διαφόρων καναλιών επικοινωνίας ως προς την υποβάθμιση του σήματος και το θόρυβο που αυτά εισάγουν. Για τη διαδικασία σχεδίασης, υλοποίησης και ελέγχου του συστήματος, καθώς και για την εκτέλεση των πειραμάτων χρησιμοποιήθηκε η αναπτυξιακή πλατφόρμα ZedBoard. Στο πρώτο μέ- ρος της εργασίας παρουσιάζονται και αναλύονται τα μοντέλα των υποσυστημάτων που απαρτίζουν το κανάλι, καθώς και η υλοποίησή τους σε λογισμικό και υλικό. Οι δύο κύ- ριες μονάδες επεξεργασίας στο κανάλι είναι ένα FIR φίλτρο και μία γεννήτρια θορύβου. Το φίλτρο χρησιμοποιείται ως το στοιχείο που υποβαθμίζει το σήμα εισόδου, ενώ η γεννήτρια θορύβου εισάγει το τυχαίο σήμα στο κανάλι επικοινωνίας. Στο δεύτερο μέρος της εργασίας αναλύεται η αρχιτεκτονική του τελικού συστήματος, οι διεπαφές Ε/Ε που χρησιμοποιήθηκαν καθώς και η λογική ελέγχου που ακολουθήθηκε. Τέλος, περιγράφουμε την επικοινωνία και τη λογική ελέγχου του συστήματος, σε επίπεδο εντολών από το περιβάλλον της MATLAB. / The purpose of this thesis is to study and implement a simulation and emulation system of the characteristics of different communications channels concerning the degradation of the signal and the noise they introduce. For the process of design, implementation and monitoring of the system as well as to perform the experiment the ZedBoard development platform was used.In the first part we present and analyze the models of the subsystems which constitute the communication channel and also their implementation in software and hardware. The two main processing units in the channel is a FIR filter and a noise generator. The filter is used as the element that lowers the power of the input signal and the noise generator introduces the random signal to the communication channel.In the second part we analyze the architecture of the final system, the I / O interfaces used and the control logic followed.Finally, we describe the communication and control logic of the system. The commands used for this purpose are developed using the computing environment of MATLAB.

The main issue in this thesis is to minimize the energy consumption per operation for the arithmetic parts of DSP circuits, such as digital filters. More specific, the focus is on single- and multiple-constant multiplication using serial arithmetic. The possibility to reduce the complexity and energy consumption is investigated. The main difference between serial and parallel arithmetic, which is of interest here, is that a shift operation in serial arithmetic require a flip-flop, while it can be hardwired in parallel arithmetic. The possible ways to connect a certain number of adders is limited, i.e., for single-constant multiplication, the number of possible structures is limited for a given number of adders. Furthermore, for each structure there is a limited number of ways to place the shift operations. Hence, it is possible to find the best solution for each constant, in terms of complexity, by an exhaustive search. Methods to bound the search space are discussed. We show that it is possible to save both adders and shifts compared to CSD serial/parallel multipliers. Besides complexity, throughput is also considered by defining structures where the critical path, for bit-serial arithmetic, is no longer than one full adder. Two algorithms for the design of multiple-constant multiplication using serial arithmetic are proposed. The difference between the proposed design algorithms is the trade-offs between adders and shifts. For both algorithms, the total complexity is decreased compared to an algorithm for parallel arithmetic. The impact of the digit-size, i.e., the number of bits to be processed in parallel, in FIR filters is studied. Two proposed multiple-constant multiplication algorithms are compared to an algorithm for parallel arithmetic and separate realization of the multipliers. The results provide some guidelines for designing low power multiple-constant multiplication algorithms for FIR filters implemented using digit-serial arithmetic. A method for computing the number of logic switchings in bit-serial constant multipliers is proposed. The average switching activity in all possible multiplier structures with up to four adders is determined. Hence, it is possible to reduce the switching activity by selecting the best structure for any given constant. In addition, a simplified method for computing the switching activity in constant serial/parallel multipliers is presented. Here it is possible to reduce the energy consumption by selecting the best signed-digit representation of the constant. Finally, a data dependent switching activity model is proposed for ripple-carry adders. For most applications, the input data is correlated, while previous estimations assumed un-correlated data. Hence, the proposed method may be included in high-level power estimation to obtain more accurate estimates. In addition, the model can be used as cost function in multiple-constant multiplication algorithms. A modified model based on word-level statistics, which is accurate in estimating the switching activity when real world signals are applied, is also presented. / Report code: LiU-Tek-Lic-2006:30.

Κατά τις δύο τελευταίες δεκαετίες έχουν αναπτυχθεί ενσωματωμένα συστήματα λήψης σημάτων φυσιολογίας που είναι ελαφριά, μικρά και ικανά να καταγράφουν σύνθετα σήματα για περισσότερες από 48 ώρες. Αυτά τα συστήματα χρησιμοποιούνται στις μελέτες ηλεκτροκαρδιογραφίας (ECG) για να εντοπίζουν σποραδικές καρδιακές αρρυθμίες ή ανωμαλίες στην καρδιακή λειτουργία, που συχνά σχετίζονται με τις εντάσεις της καθημερινότητας. Σήμερα τα καρδιακά σήματα καταγράφονται σε κάρτες μνήμης και μπορούν εύκολα να μεταφερθούν για ανάλυση και επεξεργασία. Με την εξέλιξη της τεχνολογίας, οι κατασκευαστές ιατρικού εξοπλισμού περιόρισαν δραστικά το μέγεθος και την κατανάλωση ενέργειας των συσκευών καταγραφής ΗΚΓ, έτσι ώστε αυτές να αποκτήσουν αυτονομία. Στην εργασία αυτή θα παρουσιαστεί ένα ενσωματωμένο σύστημα καταγραφής, αποθήκευσης και επεξεργασίας ηλεκτροκαρδιογραφικών σημάτων, ώστε να επιτυγχάνεται η παρακολούθηση των ζωτικών ενδείξεων ασθενών με αρρυθμίες και καρδιακή ανεπάρκεια Η εργασία αυτή χωρίζεται ουσιαστικά σε έξι τμήματα. Το πρώτο τμήμα ασχολείται με την φυσιολογία της καρδιάς, η οποία αποτελεί την πηγή του ηλεκτροκαρδιογραφήματος, καθώς και με την δομή ενός ηλεκτροκαρ-διογράφου και τους τρόπους με τους οποίους μπορούμε να το πάρουμε από τα διάφορα σημεία του ανθρώπινου σώματος. Τα επόμενα δύο τμήματα που ακολουθούν αφορούν την χρήση και τις δυνατότητες των ενσωματωμένων συστημάτων και μικροελεγκτών με έμφαση στην παρουσίαση του μικροελεγκτή (ADuC 7026) και των περιφερειακών του που θα χρησιμοποιηθούν για την υλοποίηση. Παράλληλα αναλύεται το περιβάλλον μVision της Keil το οποίο παρέχει τη δυνατότητα εξομοίωσης του μικροελεγκτή μας έχοντας στη διαθεσή μας μηδενικό υλικό. Το τρίτο τμήμα συνοψίζει κάποιες βασικές λειτουργίες προγραμματισμού και δυνατότητες που παρουσιάζει ο ADuC 7026 της Analog Devices. Το τέταρτο τμήμα ασχολείται με μεθόδους ψηφιακής επεξεργασίας σημάτων χαμηλής συχνότητας για την απομάκρυνση του θορύβου και την αύξηση της ευκρίνειας των αποτελεσμάτων. Τα δύο τελευταία τμήματα περιέχουν αναλυτικά τις μεθόδους επεξεργασίας που χρησιμοποιήθηκαν για τον προγραμματισμό του μικροελεγκτή και παραθέτονται τα αντίστοιχα αποτελέσματα. Για την υλοποίηση χρησιμοποιήθηκαν αρχικά προσεγγιστικά σήματα για τη μοντελοποίηση των πραγματικών σημάτων που προκύπτουν από την καρδιοαναπνευστική λειτουργία . Γίνεται τέλος με τη βοήθεια του matlab πλήρης αναδημιουργία του καρδιακού παλμού και εξάγονται τα κατάλληλα συμπεράσματα. Ο προγραμματισμός του μικροελεγκτή έγινε σε γλώσσα προγραμματισμού C. / During the two last decades there have been developed embedded systems , for the receive of physiology signals. that are small light and able to record composite signals for more than 48 hours. These systems are used at research on electrocardiography(ECG) for the locating of sporadic cardiac arrhythmias,or abnormal heart function, often associated with the stresses of everyday life. Nowadays, cardiac signals recorded on memory cards and can easily be transferred for analysis and processing. Through the technological evolution, medical equipment manufacturers have reduced drastically the size and power consumption of the ECG recorders, so that they can be autonomous. At this thesis, an embedded system for recording, saving and processing ECG signals is presented. The main purpose is to achieve the monitoring of vital signs of patients with arrhythmias and heart failure. The thesis is divided into six sections. The first part deals with the physiology of the heart, which is the source of the electrocardiogram and the structure of an electrocardiograph and how we can get it from different parts of the human body. The next two sections below cover the use and potential of embedded systems and microcontrollers with an emphasis on presentation of the microcontroller (ADuC 7026) and its peripherals that will be used for implementation. At the same time explaining the μVision the Keil environment which enables us to emulate the microcontroller having at our disposal zero hardware. The third section summarizes some basic functions and programming possibilities presented by ADuC 7026 of Analog Devices. The fourth part deals with methods of digital signal processing of low frequency to remove noise and increase clarity of results. The last two sections contain detailed the processes used for programming the microcontroller and presents the corresponding results. During the implementation, initially approximated signals were used for modeling of real signals arising from cardiopulmonary function. Finally, using matlab we achieve a full reconstruction of the heart beat and drew the appropriate conclusions. The programming of the microcontroller has been done in C